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Searched refs:input_rate (Results 1 – 5 of 5) sorted by relevance

/drivers/clk/mmp/
A Dclk-pll.c24 unsigned long input_rate; member
73 rate = pll->input_rate; in mmp_clk_pll_recalc_rate()
104 unsigned long input_rate, in mmp_clk_register_pll() argument
127 pll->input_rate = input_rate; in mmp_clk_register_pll()
159 clks[i].input_rate, in mmp_register_pll_clks()
A Dclk.h231 unsigned long input_rate; member
/drivers/clk/tegra/
A Dclk-pll.c531 if (sel->input_rate == 0) in _get_table_rate()
542 cfg->input_rate = sel->input_rate; in _get_table_rate()
959 unsigned long input_rate; in clk_plle_enable() local
1132 input_rate = clk_hw_get_rate(osc); in clk_pllu_enable()
1153 input_rate); in clk_pllu_enable()
1235 cfg->input_rate = parent_rate; in _calc_dynamic_ramp_rate()
1457 switch (input_rate) { in _pllcx_update_dynamic_coef()
1473 __func__, input_rate); in _pllcx_update_dynamic_coef()
1616 unsigned long input_rate; in clk_plle_tegra114_enable() local
1776 input_rate); in clk_pllu_tegra114_enable()
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A Dclk-tegra210.c1111 unsigned long input_rate; in pllx_get_dyn_steps() local
1117 input_rate = 38400000; in pllx_get_dyn_steps()
1119 input_rate /= tegra_pll_get_fixed_mdiv(hw, input_rate); in pllx_get_dyn_steps()
1121 switch (input_rate) { in pllx_get_dyn_steps()
1138 __func__, input_rate); in pllx_get_dyn_steps()
1464 cfg->input_rate / cfg->m * cfg->n / in tegra210_pllx_dyn_ramp()
1510 cf = input_rate / cfg->m; in tegra210_pll_fixed_mdiv_cfg()
1514 cfg->output_rate = input_rate; in tegra210_pll_fixed_mdiv_cfg()
1532 cfg->input_rate = input_rate; in tegra210_pll_fixed_mdiv_cfg()
2900 if (fentry->input_rate == pll_ref_freq) in tegra210_enable_pllu()
[all …]
A Dclk.h165 unsigned long input_rate; member
906 u16 tegra_pll_get_fixed_mdiv(struct clk_hw *hw, unsigned long input_rate);

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