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Searched refs:instrs (Results 1 – 25 of 39) sorted by relevance

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/drivers/mtd/nand/raw/
A Dnand_base.c1175 instrs[1].ctx.addr.naddrs++; in nand_sp_exec_read_page_op()
1212 instrs[1].ctx.addr.naddrs++; in nand_lp_exec_read_page_op()
1552 instrs); in nand_exec_prog_page_op()
1589 op.instrs++; in nand_exec_prog_page_op()
1976 instrs); in nand_erase_op()
2459 instr = &ctx->instrs[i]; in nand_op_parser_trace()
2521 .subop.instrs = op->instrs, in nand_op_parser_exec_op()
2522 .instrs = op->instrs, in nand_op_parser_exec_op()
2527 while (ctx.subop.instrs < op->instrs + op->ninstrs) { in nand_op_parser_exec_op()
2566 ctx.subop.instrs = ctx.subop.instrs + ctx.subop.ninstrs; in nand_op_parser_exec_op()
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A Dfsl_upm.c148 ret = func_exec_instr(chip, &op->instrs[i]); in fun_exec_op()
152 if (op->instrs[i].delay_ns) in fun_exec_op()
153 ndelay(op->instrs[i].delay_ns); in fun_exec_op()
A Dnand_hynix.c74 struct nand_op_instr instrs[] = { in hynix_nand_cmd_op() local
77 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in hynix_nand_cmd_op()
92 struct nand_op_instr instrs[] = { in hynix_nand_reg_write_op() local
96 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in hynix_nand_reg_write_op()
A Darasan-nand-controller.c615 instr = &subop->instrs[op_id]; in anfc_parse_instructions()
768 if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_RNDOUT && in anfc_data_read_type_exec()
769 subop->instrs[2].ctx.cmd.opcode == NAND_CMD_RNDOUTSTART) in anfc_data_read_type_exec()
820 if (subop->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS) in anfc_status_type_exec()
828 memcpy(subop->instrs[1].ctx.data.buf.in, &tmp, 1); in anfc_status_type_exec()
917 instr = &op->instrs[op_id]; in anfc_check_op()
950 op->instrs[0].type == NAND_OP_CMD_INSTR && in anfc_check_op()
951 op->instrs[0].ctx.cmd.opcode != NAND_CMD_STATUS && in anfc_check_op()
952 op->instrs[1].type == NAND_OP_DATA_IN_INSTR) in anfc_check_op()
A Dgpio.c151 ret = gpio_nand_exec_instr(chip, &op->instrs[i]); in gpio_nand_exec_op()
155 if (op->instrs[i].delay_ns) in gpio_nand_exec_op()
156 ndelay(op->instrs[i].delay_ns); in gpio_nand_exec_op()
A Dnand_toshiba.c37 struct nand_op_instr instrs[] = { in toshiba_nand_benand_read_eccstatus_op() local
42 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in toshiba_nand_benand_read_eccstatus_op()
A Dnand_macronix.c264 struct nand_op_instr instrs[] = { in nand_power_down_op() local
268 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in nand_power_down_op()
A Dams-delta.c151 for (instr = op->instrs; instr < op->instrs + op->ninstrs; instr++) { in gpio_nand_exec_op()
A Dcadence-nand-controller.c2050 instr = &subop->instrs[op_id]; in cadence_nand_cmd_opcode()
2084 instr = &subop->instrs[op_id]; in cadence_nand_cmd_address()
2118 if (subop->instrs[0].ctx.cmd.opcode == NAND_CMD_ERASE1) { in cadence_nand_cmd_erase()
2125 instr = &subop->instrs[1]; in cadence_nand_cmd_erase()
2144 .instrs = &subop->instrs[op_id], in cadence_nand_cmd_erase()
2165 instr = &subop->instrs[op_id]; in cadence_nand_cmd_data()
2231 const struct nand_op_instr *instr = &subop->instrs[op_id]; in cadence_nand_cmd_waitrdy()
A Dtechnologic-nand-controller.c122 ret = ts72xx_nand_exec_instr(chip, &op->instrs[i]); in ts72xx_nand_exec_op()
A Ddiskonchip.c348 struct nand_op_instr instrs[] = { in doc200x_readid() local
354 struct nand_operation op = NAND_OPERATION(cs, instrs); in doc200x_readid()
583 doc200x_exec_instr(this, &op->instrs[i]); in doc200x_exec_op()
655 doc2001plus_exec_instr(this, &op->instrs[i]); in doc2001plus_exec_op()
A Dau1550nd.c227 ret = au1550nd_exec_instr(this, &op->instrs[i]); in au1550nd_exec_op()
A Dqcom_nandc.c1612 instr = &subop->instrs[op_id]; in qcom_parse_instructions()
1808 int instrs = 1; in qcom_misc_cmd_type_exec() local
1822 instrs = 3; in qcom_misc_cmd_type_exec()
1837 qcom_write_reg_dma(nandc, &nandc->regs->cmd, NAND_FLASH_CMD, instrs, NAND_BAM_NEXT_SGL); in qcom_misc_cmd_type_exec()
1995 instr = &op->instrs[op_id]; in qcom_check_op()
A Dcs553x_nand.c206 ret = cs553x_exec_instr(cs553x, &op->instrs[i]); in cs553x_exec_op()
A Dloongson1-nand-controller.c168 const struct nand_op_instr *instr = &subop->instrs[op_id]; in ls1x_nand_parse_instructions()
559 const struct nand_op_instr *instr = &op->instrs[op_id]; in ls1x_nand_check_op()
A Dmxic_nand.c402 instr = &op->instrs[op_id]; in mxic_nfc_exec_op()
A Dintel-nand-controller.c526 instr = &op->instrs[op_id]; in ebu_nand_exec_op()
A Dmeson_nand.c1010 instr = &op->instrs[op_id]; in meson_nfc_check_op()
1047 instr = &op->instrs[op_id]; in meson_nfc_exec_op()
A Dmarvell_nand.c1727 instr = &subop->instrs[op_id]; in marvell_nfc_parse_instructions()
1909 switch (subop->instrs[0].type) { in marvell_nfc_naked_access_exec()
1956 if (subop->instrs[0].type == NAND_OP_DATA_OUT_INSTR) { in marvell_nfc_naked_access_exec()
A Ddavinci_nand.c812 ret = davinci_nand_exec_instr(info, &op->instrs[i]); in davinci_nand_exec_op()
A Dvf610_nfc.c355 return &subop->instrs[*op_id]; in vf610_get_next_instr()
/drivers/gpu/drm/panthor/
A Dpanthor_sched.c2962 instrs->count = ALIGN(instrs->count, NUM_INSTRS_PER_CACHE_LINE); in copy_instrs_to_ringbuf()
2963 size = instrs->count * sizeof(u64); in copy_instrs_to_ringbuf()
3075 instrs->count = 0; in prepare_job_instrs()
3083 ARRAY_SIZE(instrs->buffer), in prepare_job_instrs()
3092 instrs->buffer[instrs->count++] = instr_seq[i].instr; in prepare_job_instrs()
3096 memset(&instrs->buffer[instrs->count], 0, in prepare_job_instrs()
3097 (pad - instrs->count) * sizeof(instrs->buffer[0])); in prepare_job_instrs()
3098 instrs->count = pad; in prepare_job_instrs()
3108 prepare_job_instrs(&params, &instrs); in calc_job_credits()
3109 return instrs.count; in calc_job_credits()
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/drivers/mtd/nand/raw/ingenic/
A Dingenic_nand_drv.c327 ret = ingenic_nand_exec_instr(chip, cs, &op->instrs[i]); in ingenic_nand_exec_op()
331 if (op->instrs[i].delay_ns) in ingenic_nand_exec_op()
332 ndelay(op->instrs[i].delay_ns); in ingenic_nand_exec_op()
/drivers/mtd/nand/raw/brcmnand/
A Dbrcmnand.c2459 const struct nand_op_instr *instr = &op->instrs[i]; in brcmnand_exec_instr()
2471 ((i == (op->ninstrs - 2)) && (op->instrs[i + 1].type == NAND_OP_WAITRDY_INSTR)); in brcmnand_exec_instr()
2517 op->instrs[0].type == NAND_OP_CMD_INSTR && in brcmnand_op_is_status()
2518 op->instrs[0].ctx.cmd.opcode == NAND_CMD_STATUS && in brcmnand_op_is_status()
2519 op->instrs[1].type == NAND_OP_DATA_IN_INSTR) in brcmnand_op_is_status()
2528 op->instrs[0].type == NAND_OP_CMD_INSTR && in brcmnand_op_is_reset()
2529 op->instrs[0].ctx.cmd.opcode == NAND_CMD_RESET && in brcmnand_op_is_reset()
2530 op->instrs[1].type == NAND_OP_WAITRDY_INSTR) in brcmnand_op_is_reset()
2566 instr = &op->instrs[i]; in brcmnand_check_instructions_legacy()
2599 instr = &op->instrs[i]; in brcmnand_exec_instructions_legacy()
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/drivers/mtd/nand/raw/atmel/
A Dnand-controller.c623 ret = atmel_smc_nand_exec_instr(nand, &op->instrs[i]); in atmel_smc_nand_exec_op()
643 const struct nand_op_instr *instr = &subop->instrs[i]; in atmel_hsmc_exec_cmd_addr()
663 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_rw()
681 const struct nand_op_instr *instr = subop->instrs; in atmel_hsmc_exec_waitrdy()

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