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Searched refs:intel_de_posting_read (Results 1 – 25 of 34) sorted by relevance

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/drivers/gpu/drm/i915/display/
A Dintel_fdi.c497 intel_de_posting_read(display, reg); in intel_fdi_normal_train()
549 intel_de_posting_read(display, reg); in ilk_fdi_link_train()
630 intel_de_posting_read(display, reg); in gen6_fdi_link_train()
659 intel_de_posting_read(display, reg); in gen6_fdi_link_train()
710 intel_de_posting_read(display, reg); in gen6_fdi_link_train()
767 intel_de_posting_read(display, reg); in ivb_manual_fdi_link_train()
809 intel_de_posting_read(display, reg); in ivb_manual_fdi_link_train()
1039 intel_de_posting_read(display, reg); in ilk_fdi_pll_enable()
1044 intel_de_posting_read(display, reg); in ilk_fdi_pll_enable()
1094 intel_de_posting_read(display, reg); in ilk_fdi_disable()
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A Dg4x_hdmi.c63 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in intel_hdmi_prepare()
232 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in g4x_hdmi_enable_port()
295 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
297 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
310 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
317 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
319 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in ibx_enable_hdmi()
357 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
364 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in cpt_enable_hdmi()
394 intel_de_posting_read(display, intel_hdmi->hdmi_reg); in intel_disable_hdmi()
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A Dg4x_dp.c216 intel_de_posting_read(display, DP_A); in ilk_edp_pll_on()
231 intel_de_posting_read(display, DP_A); in ilk_edp_pll_on()
249 intel_de_posting_read(display, DP_A); in ilk_edp_pll_off()
436 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
440 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
460 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
464 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_link_down()
611 intel_de_posting_read(display, intel_dp->output_reg); in cpt_set_link_train()
639 intel_de_posting_read(display, intel_dp->output_reg); in g4x_set_link_train()
661 intel_de_posting_read(display, intel_dp->output_reg); in intel_dp_enable_port()
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A Dintel_fifo_underrun.c107 intel_de_posting_read(display, reg); in i9xx_check_fifo_underruns()
126 intel_de_posting_read(display, reg); in i9xx_set_fifo_underrun_reporting()
158 intel_de_posting_read(display, GEN7_ERR_INT); in ivb_check_fifo_underruns()
223 intel_de_posting_read(display, SERR_INT); in cpt_check_pch_fifo_underruns()
A Dintel_pps.c154 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
157 intel_de_posting_read(display, intel_dp->output_reg); in vlv_power_sequencer_kick()
774 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_on_unlocked()
845 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_vdd_off_sync_unlocked()
986 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1002 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1014 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_on_unlocked()
1061 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_off_unlocked()
1107 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_on()
1128 intel_de_posting_read(display, pp_ctrl_reg); in intel_pps_backlight_off()
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A Dintel_hdmi.c314 intel_de_posting_read(display, reg); in ibx_write_infoframe()
392 intel_de_posting_read(display, reg); in cpt_write_infoframe()
464 intel_de_posting_read(display, reg); in vlv_write_infoframe()
901 intel_de_posting_read(display, reg); in g4x_set_infoframes()
921 intel_de_posting_read(display, reg); in g4x_set_infoframes()
1073 intel_de_posting_read(display, reg); in ibx_set_infoframes()
1094 intel_de_posting_read(display, reg); in ibx_set_infoframes()
1143 intel_de_posting_read(display, reg); in cpt_set_infoframes()
1201 intel_de_posting_read(display, reg); in vlv_set_infoframes()
1231 intel_de_posting_read(display, reg); in intel_hdmi_fastset_infoframes()
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A Dintel_pch_refclk.c619 intel_de_posting_read(display, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
638 intel_de_posting_read(display, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
649 intel_de_posting_read(display, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
663 intel_de_posting_read(display, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
A Dintel_pipe_crc.c618 intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe)); in intel_crtc_set_crc_source()
653 intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe)); in intel_crtc_enable_pipe_crc()
669 intel_de_posting_read(display, PIPE_CRC_CTL(display, pipe)); in intel_crtc_disable_pipe_crc()
A Dintel_dkl_phy.c114 intel_de_posting_read(display, DKL_REG_MMIO(reg)); in intel_dkl_phy_posting_read()
A Dintel_vga.c76 intel_de_posting_read(display, vga_reg); in intel_vga_disable()
A Dintel_backlight.c512 intel_de_posting_read(display, BLC_PWM_PCH_CTL1); in lpt_enable_backlight()
551 intel_de_posting_read(display, BLC_PWM_CPU_CTL2); in pch_enable_backlight()
565 intel_de_posting_read(display, BLC_PWM_PCH_CTL1); in pch_enable_backlight()
596 intel_de_posting_read(display, BLC_PWM_CTL); in i9xx_enable_backlight()
641 intel_de_posting_read(display, BLC_PWM_CTL2); in i965_enable_backlight()
675 intel_de_posting_read(display, VLV_BLC_PWM_CTL2(pipe)); in vlv_enable_backlight()
726 intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller)); in bxt_enable_backlight()
757 intel_de_posting_read(display, BXT_BLC_PWM_CTL(panel->backlight.controller)); in cnp_enable_backlight()
A Dintel_dpll_mgr.c580 intel_de_posting_read(display, PCH_DPLL(id)); in ibx_pch_dpll_enable()
589 intel_de_posting_read(display, PCH_DPLL(id)); in ibx_pch_dpll_enable()
599 intel_de_posting_read(display, PCH_DPLL(id)); in ibx_pch_dpll_disable()
702 intel_de_posting_read(display, WRPLL_CTL(id)); in hsw_ddi_wrpll_enable()
713 intel_de_posting_read(display, SPLL_CTL); in hsw_ddi_spll_enable()
723 intel_de_posting_read(display, WRPLL_CTL(id)); in hsw_ddi_wrpll_disable()
739 intel_de_posting_read(display, SPLL_CTL); in hsw_ddi_spll_disable()
1377 intel_de_posting_read(display, DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
1392 intel_de_posting_read(display, regs[id].cfgcr1); in skl_ddi_pll_enable()
1419 intel_de_posting_read(display, regs[id].ctl); in skl_ddi_pll_disable()
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A Dintel_dvo.c197 intel_de_posting_read(display, DVO(port)); in intel_disable_dvo()
214 intel_de_posting_read(display, DVO(port)); in intel_enable_dvo()
A Dintel_dpll.c1849 intel_de_posting_read(display, DPLL(display, pipe)); in i9xx_enable_pll()
1867 intel_de_posting_read(display, DPLL(display, pipe)); in i9xx_enable_pll()
1990 intel_de_posting_read(display, DPLL(display, pipe)); in _vlv_enable_pll()
2019 intel_de_posting_read(display, DPLL_MD(display, pipe)); in vlv_enable_pll()
2187 intel_de_posting_read(display, DPLL_MD(display, pipe)); in chv_enable_pll()
2242 intel_de_posting_read(display, DPLL(display, pipe)); in vlv_disable_pll()
2260 intel_de_posting_read(display, DPLL(display, pipe)); in chv_disable_pll()
2286 intel_de_posting_read(display, DPLL(display, pipe)); in i9xx_disable_pll()
A Dintel_crt.c509 intel_de_posting_read(display, crt->adpa_reg); in ilk_crt_detect_hotplug()
731 intel_de_posting_read(display, in intel_crt_load_detect()
973 intel_de_posting_read(display, crt->adpa_reg); in intel_crt_reset()
A Dintel_de.h67 intel_de_posting_read(struct intel_display *display, i915_reg_t reg) in intel_de_posting_read() function
A Dintel_display_irq.c151 intel_de_posting_read(display, DEIMR); in ilk_update_display_irq()
193 intel_de_posting_read(display, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
225 intel_de_posting_read(display, GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
265 intel_de_posting_read(display, SDEIMR); in ibx_display_interrupt_update()
343 intel_de_posting_read(display, reg); in i915_enable_pipestat()
367 intel_de_posting_read(display, reg); in i915_disable_pipestat()
A Dhsw_ips.c86 intel_de_posting_read(display, IPS_CTL); in hsw_ips_disable()
A Dintel_display_power.c1074 intel_de_posting_read(display, reg); in gen9_dbuf_slice_set()
1265 intel_de_posting_read(display, D_COMP_BDW); in hsw_write_dcomp()
1299 intel_de_posting_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1315 intel_de_posting_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1343 intel_de_posting_read(display, LCPLL_CTL); in hsw_restore_lcpll()
A Dintel_lvds.c329 intel_de_posting_read(display, lvds_encoder->reg); in intel_enable_lvds()
352 intel_de_posting_read(display, lvds_encoder->reg); in intel_disable_lvds()
A Dicl_dsi.c370 intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
376 intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port)); in gen11_dsi_program_esc_clk_div()
383 intel_de_posting_read(display, ADL_MIPIO_DW(port, 8)); in gen11_dsi_program_esc_clk_div()
680 intel_de_posting_read(display, ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
A Dintel_gmbus.c291 intel_de_posting_read(display, bus->gpio_reg); in set_clock()
308 intel_de_posting_read(display, bus->gpio_reg); in set_data()
A Di9xx_wm.c159 intel_de_posting_read(display, FW_BLC_SELF_VLV); in _intel_set_memory_cxsr()
163 intel_de_posting_read(display, FW_BLC_SELF); in _intel_set_memory_cxsr()
172 intel_de_posting_read(display, DSPFW3(display)); in _intel_set_memory_cxsr()
178 intel_de_posting_read(display, FW_BLC_SELF); in _intel_set_memory_cxsr()
189 intel_de_posting_read(display, INSTPM); in _intel_set_memory_cxsr()
822 intel_de_posting_read(display, DSPFW1(display)); in g4x_write_wm_values()
901 intel_de_posting_read(display, DSPFW1(display)); in vlv_write_wm_values()
A Dintel_hotplug_irq.c958 intel_de_posting_read(display, GEN11_DE_HPD_IMR); in gen11_hpd_irq_setup()
1144 intel_de_posting_read(display, PICAINTERRUPT_IMR); in xelpdp_hpd_irq_setup()
A Dvlv_dsi_pll.c547 intel_de_posting_read(display, BXT_DSI_PLL_CTL); in bxt_dsi_pll_enable()

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