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Searched refs:intel_de_read (Results 1 – 25 of 67) sorted by relevance

123

/drivers/gpu/drm/i915/display/
A Dintel_fdi.c42 cur_state = intel_de_read(display, in assert_fdi_tx()
475 temp = intel_de_read(display, reg); in intel_fdi_normal_train()
486 temp = intel_de_read(display, reg); in intel_fdi_normal_train()
527 temp = intel_de_read(display, reg); in ilk_fdi_link_train()
531 intel_de_read(display, reg); in ilk_fdi_link_train()
536 temp = intel_de_read(display, reg); in ilk_fdi_link_train()
544 temp = intel_de_read(display, reg); in ilk_fdi_link_train()
625 temp = intel_de_read(display, reg); in gen6_fdi_link_train()
635 temp = intel_de_read(display, reg); in gen6_fdi_link_train()
649 temp = intel_de_read(display, reg); in gen6_fdi_link_train()
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A Dintel_pch_display.c111 val = intel_de_read(display, PCH_TRANSCONF(pipe)); in assert_pch_transcoder_disabled()
121 u32 val = intel_de_read(display, hdmi_reg); in ibx_sanitize_pch_hdmi_port()
140 u32 val = intel_de_read(display, dp_reg); in ibx_sanitize_pch_dp_port()
263 val = intel_de_read(display, reg); in ilk_enable_pch_transcoder()
276 val = intel_de_read(display, reg); in ilk_enable_pch_transcoder()
382 temp = intel_de_read(display, PCH_DPLL_SEL); in ilk_pch_enable()
424 temp = intel_de_read(display, reg); in ilk_pch_enable()
511 tmp = intel_de_read(display, FDI_RX_CTL(pipe)); in ilk_pch_get_config()
525 tmp = intel_de_read(display, PCH_DPLL_SEL); in ilk_pch_get_config()
566 pipeconf_val = intel_de_read(display, in lpt_enable_pch_transcoder()
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A Di9xx_display_sr.c22 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
23 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
26 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
29 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
32 display->restore.saveSWF0[i] = intel_de_read(display, SWF0(display, i)); in i9xx_display_save_swf()
33 display->restore.saveSWF1[i] = intel_de_read(display, SWF1(display, i)); in i9xx_display_save_swf()
36 display->restore.saveSWF3[i] = intel_de_read(display, SWF3(display, i)); in i9xx_display_save_swf()
74 display->restore.saveDSPARB = intel_de_read(display, DSPARB(display)); in i9xx_display_sr_save()
A Dintel_crt.c95 val = intel_de_read(display, adpa_reg); in intel_crt_port_enabled()
132 tmp = intel_de_read(display, crt->adpa_reg); in intel_crt_get_flags()
514 adpa = intel_de_read(display, crt->adpa_reg); in ilk_crt_detect_hotplug()
563 adpa = intel_de_read(display, crt->adpa_reg); in valleyview_crt_detect_hotplug()
709 save_bclrpat = intel_de_read(display, in intel_crt_load_detect()
711 save_vtotal = intel_de_read(display, in intel_crt_load_detect()
713 vblank = intel_de_read(display, in intel_crt_load_detect()
726 u32 transconf = intel_de_read(display, in intel_crt_load_detect()
754 u32 vsync = intel_de_read(display, in intel_crt_load_detect()
969 adpa = intel_de_read(display, crt->adpa_reg); in intel_crt_reset()
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A Dintel_backlight.c257 tmp = intel_de_read(display, BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
357 tmp = intel_de_read(display, BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
577 ctl = intel_de_read(display, BLC_PWM_CTL); in i9xx_enable_backlight()
619 ctl2 = intel_de_read(display, BLC_PWM_CTL2); in i965_enable_backlight()
690 val = intel_de_read(display, UTIL_PIN_CTL); in bxt_enable_backlight()
1326 ctl = intel_de_read(display, BLC_PWM_CTL); in i9xx_setup_backlight()
1368 ctl2 = intel_de_read(display, BLC_PWM_CTL2); in i965_setup_backlight()
1372 ctl = intel_de_read(display, BLC_PWM_CTL); in i965_setup_backlight()
1436 pwm_ctl = intel_de_read(display, in bxt_setup_backlight()
1441 val = intel_de_read(display, UTIL_PIN_CTL); in bxt_setup_backlight()
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A Dintel_combo_phy.c62 val = intel_de_read(display, ICL_PORT_COMP_DW3(phy)); in icl_get_procmon_ref_values()
98 u32 val = intel_de_read(display, reg); in check_phy_reg()
156 return intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT; in icl_combo_phy_enabled()
158 return !(intel_de_read(display, ICL_PHY_MISC(phy)) & in icl_combo_phy_enabled()
160 (intel_de_read(display, ICL_PORT_COMP_DW0(phy)) & COMP_INIT); in icl_combo_phy_enabled()
337 val = intel_de_read(display, ICL_PHY_MISC(phy)); in icl_combo_phys_init()
351 val = intel_de_read(display, ICL_PORT_TX_DW8_LN(0, phy)); in icl_combo_phys_init()
357 val = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy)); in icl_combo_phys_init()
A Dintel_display_power_well.c608 val = intel_de_read(display, regs->driver); in hsw_power_well_enabled()
618 val |= intel_de_read(display, regs->bios); in hsw_power_well_enabled()
631 intel_de_read(display, DC_STATE_EN) & in assert_can_enable_dc9()
635 intel_de_read(display, HSW_PWR_WELL_CTL2) & in assert_can_enable_dc9()
657 intel_de_read(display, DC_STATE_EN) & in assert_can_disable_dc9()
685 v = intel_de_read(display, DC_STATE_EN); in gen9_write_dc_state()
784 val = intel_de_read(display, DC_STATE_EN); in gen9_set_dc_state()
842 (intel_de_read(display, DC_STATE_EN) & in assert_can_enable_dc5()
870 (intel_de_read(display, UTIL_PIN_CTL) & in assert_can_enable_dc6()
875 (intel_de_read(display, DC_STATE_EN) & in assert_can_enable_dc6()
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A Dintel_display_irq.c185 old_val = intel_de_read(display, GEN8_DE_PORT_IMR); in bdw_update_port_irq()
252 u32 sdeimr = intel_de_read(display, SDEIMR); in ibx_display_interrupt_update()
687 intel_de_read(display, FDI_RX_IIR(pipe))); in ibx_irq_handler()
775 u32 serr_int = intel_de_read(display, SERR_INT); in cpt_serr_int_handler()
818 intel_de_read(display, FDI_RX_IIR(pipe))); in cpt_irq_handler()
911 u32 pch_iir = intel_de_read(display, SDEIIR); in ilk_display_irq_handler()
966 u32 pch_iir = intel_de_read(display, SDEIIR); in ivb_display_irq_handler()
1318 *pch_iir = intel_de_read(display, SDEIIR); in gen8_read_and_ack_pch_irqs()
1797 tmp = intel_de_read(display, DPINVGTT); in vlv_page_table_error_irq_ack()
1836 *eir = intel_de_read(display, VLV_EIR); in vlv_display_error_irq_ack()
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A Dintel_pps.c302 u32 port_sel = intel_de_read(display, in vlv_initial_pps_pipe()
624 intel_de_read(display, pp_stat_reg), in wait_panel_status()
625 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
632 intel_de_read(display, pp_stat_reg), in wait_panel_status()
633 intel_de_read(display, pp_ctrl_reg)); in wait_panel_status()
779 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_on_unlocked()
780 intel_de_read(display, pp_ctrl_reg)); in intel_pps_vdd_on_unlocked()
852 intel_de_read(display, pp_stat_reg), in intel_pps_vdd_off_sync_unlocked()
1676 intel_de_read(display, regs.pp_on), in pps_init_registers()
1677 intel_de_read(display, regs.pp_off), in pps_init_registers()
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A Dicl_dsi.c189 tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans)); in dsi_send_pkt_hdr()
301 dss_ctl1 = intel_de_read(display, dss_ctl1_reg); in configure_dual_link_mode()
459 tmp = intel_de_read(display, in gen11_dsi_config_phy_lanes_sequence()
615 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); in gen11_dsi_gate_clocks()
631 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); in gen11_dsi_ungate_clocks()
647 tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0); in gen11_dsi_is_clock_enabled()
668 val = intel_de_read(display, ICL_DPCLKA_CFGCR0); in gen11_dsi_map_pll()
808 tmp = intel_de_read(display, in gen11_dsi_configure_transcoder()
1100 tmp = intel_de_read(display, UTIL_PIN_CTL); in gen11_dsi_config_util_pin()
1335 tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans)); in gen11_dsi_deconfigure_trancoder()
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A Dintel_dpll_mgr.c542 val = intel_de_read(display, PCH_DPLL(id)); in ibx_pch_dpll_get_hw_state()
763 val = intel_de_read(display, WRPLL_CTL(id)); in hsw_ddi_wrpll_get_hw_state()
784 val = intel_de_read(display, SPLL_CTL); in hsw_ddi_spll_get_hw_state()
1445 val = intel_de_read(display, regs[id].ctl); in skl_ddi_pll_get_hw_state()
1449 val = intel_de_read(display, DPLL_CTRL1); in skl_ddi_pll_get_hw_state()
1484 val = intel_de_read(display, regs[id].ctl); in skl_ddi_dpll0_get_hw_state()
1488 val = intel_de_read(display, DPLL_CTRL1); in skl_ddi_dpll0_get_hw_state()
2225 hw_state->pcsdw12 = intel_de_read(display, in bxt_ddi_pll_get_hw_state()
2231 intel_de_read(display, in bxt_ddi_pll_get_hw_state()
3558 val = intel_de_read(display, enable_reg); in mg_pll_get_hw_state()
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A Dvlv_dsi.c125 u32 val = intel_de_read(display, reg); in read_data()
638 temp = intel_de_read(display, port_ctrl); in intel_dsi_port_enable()
971 enabled = intel_de_read(display, in intel_dsi_get_hw_state()
976 u32 tmp = intel_de_read(display, in intel_dsi_get_hw_state()
1051 intel_de_read(display, in bxt_dsi_get_pipe_config()
1054 intel_de_read(display, in bxt_dsi_get_pipe_config()
1057 intel_de_read(display, in bxt_dsi_get_pipe_config()
1061 hfp = intel_de_read(display, MIPI_HFP_COUNT(display, port)); in bxt_dsi_get_pipe_config()
1068 hbp = intel_de_read(display, MIPI_HBP_COUNT(display, port)); in bxt_dsi_get_pipe_config()
1331 tmp = intel_de_read(display, MIPI_CTRL(display, PORT_A)); in intel_dsi_prepare()
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A Di9xx_plane.c571 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in g4x_primary_capture_error()
583 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i965_plane_capture_error()
594 error->ctl = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i8xx_plane_capture_error()
743 val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i9xx_plane_get_hw_state()
1188 val = intel_de_read(display, DSPCNTR(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1209 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1214 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1217 offset = intel_de_read(display, in i9xx_get_initial_plane_config()
1222 base = intel_de_read(display, DSPADDR(display, i9xx_plane)); in i9xx_get_initial_plane_config()
1228 val = intel_de_read(display, PIPESRC(display, pipe)); in i9xx_get_initial_plane_config()
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A Dintel_fifo_underrun.c102 if ((intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) == 0) in i9xx_check_fifo_underruns()
128 if (old && intel_de_read(display, reg) & PIPE_FIFO_UNDERRUN_STATUS) in i9xx_set_fifo_underrun_reporting()
150 u32 err_int = intel_de_read(display, GEN7_ERR_INT); in ivb_check_fifo_underruns()
180 intel_de_read(display, GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivb_set_fifo_underrun_reporting()
214 u32 serr_int = intel_de_read(display, SERR_INT); in cpt_check_pch_fifo_underruns()
245 if (old && intel_de_read(display, SERR_INT) & in cpt_set_fifo_underrun_reporting()
A Dintel_pch_refclk.c22 if (wait_for_us(intel_de_read(display, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
28 if (wait_for_us((intel_de_read(display, SOUTH_CHICKEN2) & in lpt_fdi_reset_mphy()
238 if ((intel_de_read(display, PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) in lpt_get_iclkip()
401 u32 fuse_strap = intel_de_read(display, FUSE_STRAP); in spll_uses_pch_ssc()
402 u32 ctl = intel_de_read(display, SPLL_CTL); in spll_uses_pch_ssc()
420 u32 fuse_strap = intel_de_read(display, FUSE_STRAP); in wrpll_uses_pch_ssc()
421 u32 ctl = intel_de_read(display, WRPLL_CTL(id)); in wrpll_uses_pch_ssc()
537 temp = intel_de_read(display, PCH_DPLL(pll->info->id)); in ilk_init_pch_refclk()
558 val = intel_de_read(display, PCH_DREF_CONTROL); in ilk_init_pch_refclk()
A Dintel_tc.c304 val = intel_de_read(display, TCSS_DDI_STATUS(tc_port)); in lnl_tc_port_get_max_lane_count()
500 pch_isr = intel_de_read(display, SDEISR); in icl_tc_phy_hpd_live_status()
737 val = intel_de_read(display, PORT_TX_DFLEXDPSP(FIA1)); in tgl_tc_phy_init()
784 cpu_isr = intel_de_read(display, GEN11_DE_HPD_ISR); in adlp_tc_phy_hpd_live_status()
785 pch_isr = intel_de_read(display, SDEISR); in adlp_tc_phy_hpd_live_status()
814 val = intel_de_read(display, TCSS_DDI_STATUS(tc_port)); in adlp_tc_phy_is_ready()
847 val = intel_de_read(display, DDI_BUF_CTL(port)); in adlp_tc_phy_is_owned()
972 pica_isr = intel_de_read(display, PICAINTERRUPT_ISR); in xelpdp_tc_phy_hpd_live_status()
973 pch_isr = intel_de_read(display, SDEISR); in xelpdp_tc_phy_hpd_live_status()
1055 val = intel_de_read(display, reg); in __xelpdp_tc_phy_enable_tcss_power()
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A Dintel_flipq.c178 return intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)); in intel_flipq_current_head()
221 intel_de_read(display, PIPEDMC_FQ_RAM(flipq->start_mmioaddr, i))); in intel_flipq_dump()
229 intel_de_read(display, PIPEDMC_FPQ_CHP(crtc->pipe, flipq_id)), in intel_flipq_dump()
230 intel_de_read(display, PIPEDMC_FPQ_HP(crtc->pipe, flipq_id))); in intel_flipq_dump()
240 intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe))); in intel_flipq_dump()
242 tmp = intel_de_read(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe)); in intel_flipq_dump()
433 pts += intel_de_read(display, PIPEDMC_FPQ_TS(crtc->pipe)); in intel_flipq_add()
A Dintel_display_power.c1181 u32 val = intel_de_read(display, LCPLL_CTL); in hsw_assert_cdclk()
1253 return intel_de_read(display, D_COMP_HSW); in hsw_read_dcomp()
1255 return intel_de_read(display, D_COMP_BDW); in hsw_read_dcomp()
1284 val = intel_de_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1290 if (wait_for_us(intel_de_read(display, LCPLL_CTL) & in hsw_disable_lcpll()
1294 val = intel_de_read(display, LCPLL_CTL); in hsw_disable_lcpll()
1328 val = intel_de_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1351 val = intel_de_read(display, LCPLL_CTL); in hsw_restore_lcpll()
1361 if (wait_for_us((intel_de_read(display, LCPLL_CTL) & in hsw_restore_lcpll()
1828 u32 status = intel_de_read(display, DPIO_PHY_STATUS); in chv_phy_control_init()
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A Dintel_lvds.c91 val = intel_de_read(display, lvds_reg); in intel_lvds_port_enabled()
130 tmp = intel_de_read(display, lvds_encoder->reg); in intel_lvds_get_config()
148 tmp = intel_de_read(display, PFIT_CONTROL(display)); in intel_lvds_get_config()
161 pps->powerdown_on_reset = intel_de_read(display, in intel_lvds_pps_get_hw_state()
164 val = intel_de_read(display, PP_ON_DELAYS(display, 0)); in intel_lvds_pps_get_hw_state()
169 val = intel_de_read(display, PP_OFF_DELAYS(display, 0)); in intel_lvds_pps_get_hw_state()
173 val = intel_de_read(display, PP_DIVISOR(display, 0)); in intel_lvds_pps_get_hw_state()
215 val = intel_de_read(display, PP_CONTROL(display, 0)); in intel_lvds_pps_init_hw()
819 val = intel_de_read(display, lvds_encoder->reg); in compute_is_dual_link_lvds()
870 lvds = intel_de_read(display, lvds_reg); in intel_lvds_init()
A Dintel_cmtg.c97 val = intel_de_read(display, TRANS_DDI_FUNC_CTL2(display, trans)); in intel_cmtg_transcoder_is_secondary()
107 val = intel_de_read(display, TRANS_CMTG_CTL_A); in intel_cmtg_get_config()
111 val = intel_de_read(display, TRANS_CMTG_CTL_B); in intel_cmtg_get_config()
A Dg4x_dp.c186 bool cur_state = intel_de_read(display, DP_A) & EDP_PLL_ENABLE; in assert_edp_pll()
259 u32 val = intel_de_read(display, TRANS_DP_CTL(p)); in cpt_dp_port_selected()
283 val = intel_de_read(display, dp_reg); in g4x_dp_port_enabled()
350 tmp = intel_de_read(display, intel_dp->output_reg); in intel_dp_get_config()
355 u32 trans_dp = intel_de_read(display, in intel_dp_get_config()
421 (intel_de_read(display, intel_dp->output_reg) & in intel_dp_link_down()
671 u32 dp_reg = intel_de_read(display, intel_dp->output_reg); in intel_enable_dp()
1178 return intel_de_read(display, SDEISR) & bit; in ibx_digital_port_connected()
1201 return intel_de_read(display, PORT_HOTPLUG_STAT(display)) & bit; in g4x_digital_port_connected()
1209 return intel_de_read(display, DEISR) & bit; in ilk_digital_port_connected()
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A Dintel_tv.c919 u32 tmp = intel_de_read(display, TV_CTL); in intel_tv_get_hw_state()
1106 tv_ctl = intel_de_read(display, TV_CTL); in intel_tv_get_config()
1107 hctl1 = intel_de_read(display, TV_H_CTL_1); in intel_tv_get_config()
1108 hctl3 = intel_de_read(display, TV_H_CTL_3); in intel_tv_get_config()
1109 vctl1 = intel_de_read(display, TV_V_CTL_1); in intel_tv_get_config()
1110 vctl2 = intel_de_read(display, TV_V_CTL_2); in intel_tv_get_config()
1145 tmp = intel_de_read(display, TV_WIN_POS); in intel_tv_get_config()
1149 tmp = intel_de_read(display, TV_WIN_SIZE); in intel_tv_get_config()
1452 tv_ctl = intel_de_read(display, TV_CTL); in intel_tv_pre_enable()
1635 tv_dac = intel_de_read(display, TV_DAC); in intel_tv_detect_type()
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A Dintel_ddi.c687 ctl = intel_de_read(display, in intel_ddi_disable_transcoder_func()
821 tmp = intel_de_read(display, in intel_ddi_get_encoder_pipes()
861 tmp = intel_de_read(display, in intel_ddi_get_encoder_pipes()
1995 tmp = intel_de_read(display, DPLL_CTRL2); in skl_ddi_get_pll()
3439 val = intel_de_read(display, reg); in intel_ddi_enable_hdmi()
3926 u32 ctl2 = intel_de_read(display, in bdw_transcoder_master_readout()
3934 u32 ctl = intel_de_read(display, in bdw_transcoder_master_readout()
4058 intel_de_read(display, in intel_ddi_read_func_ctl_dp_sst()
4089 intel_de_read(display, in intel_ddi_read_func_ctl_dp_mst()
4815 return intel_de_read(display, SDEISR) & bit; in lpt_digital_port_connected()
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A Dintel_hdmi.c287 u32 val = intel_de_read(display, reg); in ibx_write_infoframe()
340 u32 val = intel_de_read(display, reg); in ibx_infoframes_enabled()
362 u32 val = intel_de_read(display, reg); in cpt_write_infoframe()
436 u32 val = intel_de_read(display, reg); in vlv_write_infoframe()
481 *data++ = intel_de_read(display, in vlv_read_infoframe()
557 *data++ = intel_de_read(display, in hsw_read_infoframe()
565 u32 val = intel_de_read(display, in hsw_infoframes_enabled()
873 u32 val = intel_de_read(display, reg); in g4x_set_infoframes()
1058 u32 val = intel_de_read(display, reg); in ibx_set_infoframes()
1116 u32 val = intel_de_read(display, reg); in cpt_set_infoframes()
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A Dintel_overlay.c336 tmp = intel_de_read(display, DOVSTA); in intel_overlay_continue()
964 tmp = intel_de_read(display, PFIT_AUTO_RATIOS(display)); in update_pfit_vscale_ratio()
966 tmp = intel_de_read(display, PFIT_PGM_RATIOS(display)); in update_pfit_vscale_ratio()
1309 attrs->gamma0 = intel_de_read(display, OGAMC0); in intel_overlay_attrs_ioctl()
1310 attrs->gamma1 = intel_de_read(display, OGAMC1); in intel_overlay_attrs_ioctl()
1311 attrs->gamma2 = intel_de_read(display, OGAMC2); in intel_overlay_attrs_ioctl()
1312 attrs->gamma3 = intel_de_read(display, OGAMC3); in intel_overlay_attrs_ioctl()
1313 attrs->gamma4 = intel_de_read(display, OGAMC4); in intel_overlay_attrs_ioctl()
1314 attrs->gamma5 = intel_de_read(display, OGAMC5); in intel_overlay_attrs_ioctl()
1495 error->dovsta = intel_de_read(display, DOVSTA); in intel_overlay_snapshot_capture()
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