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Searched refs:intel_de_rmw (Results 1 – 25 of 49) sorted by relevance

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/drivers/gpu/drm/i915/display/
A Dintel_hotplug_irq.c742 intel_de_rmw(display, PCH_PORT_HOTPLUG, in ibx_hpd_detection_setup()
751 intel_de_rmw(display, PCH_PORT_HOTPLUG, in ibx_hpd_enable_detection()
808 intel_de_rmw(display, SHOTPLUG_CTL_DDI, in icp_ddi_hpd_detection_setup()
817 intel_de_rmw(display, SHOTPLUG_CTL_DDI, in icp_ddi_hpd_enable_detection()
824 intel_de_rmw(display, SHOTPLUG_CTL_TC, in icp_tc_hpd_detection_setup()
833 intel_de_rmw(display, SHOTPLUG_CTL_TC, in icp_tc_hpd_enable_detection()
1003 intel_de_rmw(display, SHOTPLUG_CTL_DDI, in mtp_ddi_hpd_detection_setup()
1012 intel_de_rmw(display, SHOTPLUG_CTL_DDI, in mtp_ddi_hpd_enable_detection()
1019 intel_de_rmw(display, SHOTPLUG_CTL_TC, in mtp_tc_hpd_detection_setup()
1028 intel_de_rmw(display, SHOTPLUG_CTL_DDI, in mtp_tc_hpd_enable_detection()
[all …]
A Dintel_display_wa.c15 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP); in gen11_display_wa_apply()
21 intel_de_rmw(display, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0); in xe_d_display_wa_apply()
27 intel_de_rmw(display, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS); in adlp_display_wa_apply()
30 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0); in adlp_display_wa_apply()
A Dintel_fdi.c573 intel_de_rmw(display, FDI_TX_CTL(pipe), in ilk_fdi_link_train()
575 intel_de_rmw(display, FDI_RX_CTL(pipe), in ilk_fdi_link_train()
663 intel_de_rmw(display, FDI_TX_CTL(pipe), in gen6_fdi_link_train()
714 intel_de_rmw(display, FDI_TX_CTL(pipe), in gen6_fdi_link_train()
835 intel_de_rmw(display, FDI_TX_CTL(pipe), in ivb_manual_fdi_link_train()
838 intel_de_rmw(display, FDI_RX_CTL(pipe), in ivb_manual_fdi_link_train()
951 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
988 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_link_train()
1016 intel_de_rmw(display, FDI_RX_MISC(PIPE_A), in hsw_fdi_disable()
1043 intel_de_rmw(display, reg, 0, FDI_PCDCLK); in ilk_fdi_pll_enable()
[all …]
A Dintel_cmtg.c135 intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_A), in intel_cmtg_disable()
139 intel_de_rmw(display, TRANS_DDI_FUNC_CTL2(display, TRANSCODER_B), in intel_cmtg_disable()
144 intel_de_rmw(display, TRANS_CMTG_CTL_A, CMTG_ENABLE, 0); in intel_cmtg_disable()
151 intel_de_rmw(display, TRANS_CMTG_CTL_B, CMTG_ENABLE, 0); in intel_cmtg_disable()
157 intel_de_rmw(display, CMTG_CLK_SEL, clk_sel_clr, clk_sel_set); in intel_cmtg_disable()
A Dicl_dsi.c233 intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0, in icl_dsi_frame_update()
410 intel_de_rmw(display, ICL_DSI_IO_MODECTL(port), in gen11_dsi_enable_io_power()
491 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0, in gen11_dsi_voltage_swing_program_seq()
567 intel_de_rmw(display, ICL_DPHY_CHKN(phy), in gen11_dsi_setup_dphy_timings()
795 intel_de_rmw(display, in gen11_dsi_configure_transcoder()
1065 intel_de_rmw(display, DSI_HSTX_TO(dsi_trans), in gen11_dsi_setup_timeouts()
1079 intel_de_rmw(display, DSI_TA_TO(dsi_trans), in gen11_dsi_setup_timeouts()
1232 intel_de_rmw(display, CHICKEN_PAR1_1, in icl_apply_kvmr_pipe_a_wa()
1328 intel_de_rmw(display, DSI_CMD_FRMCTL(port), in gen11_dsi_deconfigure_trancoder()
1349 intel_de_rmw(display, in gen11_dsi_deconfigure_trancoder()
[all …]
A Dintel_audio.c294 intel_de_rmw(display, G4X_AUD_CNTL_ST, in g4x_audio_codec_disable()
312 intel_de_rmw(display, G4X_AUD_CNTL_ST, in g4x_audio_codec_enable()
326 intel_de_rmw(display, G4X_AUD_CNTL_ST, in g4x_audio_codec_enable()
433 intel_de_rmw(display, HSW_AUD_PIN_ELD_CP_VLD, in hsw_audio_codec_disable()
643 intel_de_rmw(display, regs.aud_config, in ibx_audio_codec_disable()
652 intel_de_rmw(display, regs.aud_cntrl_st2, in ibx_audio_codec_disable()
681 intel_de_rmw(display, regs.aud_cntrl_st2, in ibx_audio_codec_enable()
690 intel_de_rmw(display, regs.aud_config, in ibx_audio_codec_enable()
1066 intel_de_rmw(display, AUD_PIN_BUF_CTL, in intel_audio_component_get_power()
1102 intel_de_rmw(display, HSW_AUD_CHICKENBIT, in intel_audio_component_codec_wake_override()
[all …]
A Dintel_combo_phy.c87 intel_de_rmw(display, ICL_PORT_COMP_DW1(phy), in icl_set_procmon_ref_values()
305 intel_de_rmw(display, ICL_PORT_CL_DW10(phy), in intel_combo_phy_power_up_lanes()
366 intel_de_rmw(display, ICL_PORT_COMP_DW8(phy), in icl_combo_phys_init()
369 intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), 0, COMP_INIT); in icl_combo_phys_init()
370 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), in icl_combo_phys_init()
401 intel_de_rmw(display, ICL_PHY_MISC(phy), 0, in icl_combo_phys_uninit()
405 intel_de_rmw(display, ICL_PORT_COMP_DW0(phy), COMP_INIT, 0); in icl_combo_phys_uninit()
A Dvlv_dsi.c349 intel_de_rmw(display, MIPI_CTRL(display, port), in glk_dsi_enable_io()
388 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
393 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_device_ready()
517 intel_de_rmw(display, MIPI_DEVICE_READY(display, port), in glk_dsi_enter_low_power_mode()
603 intel_de_rmw(display, port_ctrl, LP_OUTPUT_HOLD, 0); in vlv_dsi_clear_device_ready()
624 intel_de_rmw(display, MIPI_CTRL(display, port), in intel_dsi_port_enable()
628 intel_de_rmw(display, VLV_CHICKEN_3, in intel_dsi_port_enable()
673 intel_de_rmw(display, port_ctrl, DPI_ENABLE, 0); in intel_dsi_port_disable()
764 intel_de_rmw(display, DSPCLK_GATE_D(display), in intel_dsi_pre_enable()
921 intel_de_rmw(display, DSPCLK_GATE_D(display), in intel_dsi_post_disable()
[all …]
A Dintel_dpio_phy.c321 intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
331 intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
345 intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane), in bxt_dpio_phy_set_signal_levels()
436 intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy), in _bxt_dpio_phy_init()
439 intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy), in _bxt_dpio_phy_init()
443 intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0, in _bxt_dpio_phy_init()
447 intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0, in _bxt_dpio_phy_init()
467 intel_de_rmw(display, BXT_PORT_REF_DW8(phy), in _bxt_dpio_phy_init()
474 intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS); in _bxt_dpio_phy_init()
483 intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0); in bxt_dpio_phy_uninit()
[all …]
A Dintel_display_power_well.c375 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC); in hsw_power_well_enable()
533 intel_de_rmw(display, DP_AUX_CH_CTL(aux_ch), in icl_tc_phy_aux_power_well_enable()
536 intel_de_rmw(display, regs->driver, in icl_tc_phy_aux_power_well_enable()
819 intel_de_rmw(display, DC_STATE_EN, DC_STATE_DC3CO_STATUS, 0); in tgl_disable_dc3co()
859 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in gen9_enable_dc5()
890 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in skl_enable_dc6()
1211 intel_de_rmw(display, DSPCLK_GATE_D(display), in vlv_init_display_clock_gating()
1326 intel_de_rmw(display, DPIO_CTL, 0, DPIO_CMNRST); in vlv_dpio_cmn_power_well_enable()
1338 intel_de_rmw(display, DPIO_CTL, DPIO_CMNRST, 0); in vlv_dpio_cmn_power_well_disable()
1853 intel_de_rmw(display, XELPDP_DP_AUX_CH_CTL(display, aux_ch), in xelpdp_aux_power_well_enable()
[all …]
A Dintel_dpt_common.c24 intel_de_rmw(display, PLANE_CHICKEN(pipe, plane_id), in intel_dpt_configure()
30 intel_de_rmw(display, CHICKEN_MISC_2, in intel_dpt_configure()
A Dintel_ddi.c1263 intel_de_rmw(display, ICL_PORT_CL_DW5(phy), in icl_combo_phy_set_signal_levels()
1350 intel_de_rmw(display, MG_CLKHUB(ln, tc_port), in icl_mg_phy_set_signal_levels()
1561 intel_de_rmw(display, reg, clk_off, 0); in _icl_ddi_enable_clock()
1571 intel_de_rmw(display, reg, 0, clk_off); in _icl_ddi_disable_clock()
1850 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, in icl_ddi_tc_enable_clock()
1864 intel_de_rmw(display, ICL_DPCLKA_CFGCR0, in icl_ddi_tc_disable_clock()
1954 intel_de_rmw(display, DPLL_CTRL2, in skl_ddi_enable_clock()
1970 intel_de_rmw(display, DPLL_CTRL2, in skl_ddi_disable_clock()
2578 intel_de_rmw(display, reg, 0, set_bits); in mtl_ddi_enable_d2d()
3075 intel_de_rmw(display, reg, clr_bits, 0); in mtl_ddi_disable_d2d()
[all …]
A Dintel_display_power.c1072 intel_de_rmw(display, reg, DBUF_POWER_REQUEST, in gen9_dbuf_slice_set()
1145 intel_de_rmw(display, DBUF_CTL_S(slice), in gen12_dbuf_slices_config()
1176 intel_de_rmw(display, MBUS_ABOX_CTL(i), mask, val); in icl_mbus_init()
1401 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in hsw_enable_pc8()
1642 intel_de_rmw(display, BW_BUDDY_CTL(i), in tgl_bw_buddy_init()
1660 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, 0, in icl_display_core_init()
1682 intel_de_rmw(display, DC_STATE_EN, in icl_display_core_init()
1714 intel_de_rmw(display, GEN11_CHICKEN_DCPR_2, 0, in icl_display_core_init()
1724 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in icl_display_core_init()
1726 intel_de_rmw(display, SOUTH_DSPCLK_GATE_D, in icl_display_core_init()
[all …]
A Dintel_pch_display.c327 intel_de_rmw(display, reg, TRANS_ENABLE, 0); in ilk_disable_pch_transcoder()
335 intel_de_rmw(display, TRANS_CHICKEN2(pipe), in ilk_disable_pch_transcoder()
465 intel_de_rmw(display, TRANS_DP_CTL(pipe), in ilk_pch_post_disable()
470 intel_de_rmw(display, PCH_DPLL_SEL, in ilk_pch_post_disable()
582 intel_de_rmw(display, LPT_TRANSCONF, TRANS_ENABLE, 0); in lpt_disable_pch_transcoder()
589 intel_de_rmw(display, TRANS_CHICKEN2(PIPE_A), TRANS_CHICKEN2_TIMING_OVERRIDE, 0); in lpt_disable_pch_transcoder()
A Dintel_dpll_mgr.c1372 intel_de_rmw(display, DPLL_CTRL1, in skl_ddi_pll_write_ctrl1()
2056 intel_de_rmw(display, BXT_PORT_PLL_ENABLE(port), in bxt_ddi_pll_enable()
2074 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 0), in bxt_ddi_pll_enable()
2078 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 1), in bxt_ddi_pll_enable()
2082 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 2), in bxt_ddi_pll_enable()
2086 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 3), in bxt_ddi_pll_enable()
2098 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 8), in bxt_ddi_pll_enable()
2101 intel_de_rmw(display, BXT_PORT_PLL(phy, ch, 9), in bxt_ddi_pll_enable()
3793 intel_de_rmw(display, div0_reg, in icl_dpll_write()
3810 intel_de_rmw(display, MG_REFCLKIN_CTL(tc_port), in icl_mg_pll_write()
[all …]
A Dintel_psr.c470 val = intel_de_rmw(display, in intel_psr_irq_handler()
1010 intel_de_rmw(display, in dg2_activate_panel_replay()
1846 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in wm_optimization_wa()
1849 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in wm_optimization_wa()
1922 intel_de_rmw(display, in intel_psr_enable_source()
1958 intel_de_rmw(display, in intel_psr_enable_source()
2100 val = intel_de_rmw(display, in intel_psr_exit()
2112 val = intel_de_rmw(display, in intel_psr_exit()
2167 intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, in intel_psr_disable_locked()
2174 intel_de_rmw(display, in intel_psr_disable_locked()
[all …]
A Dintel_dmc.c425 intel_de_rmw(display, DC_STATE_DEBUG, 0, in gen9_set_dc_state_debugmask()
472 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
476 intel_de_rmw(display, CLKGATE_DIS_PSL_EXT(pipe), in adlp_pipedmc_clock_gating_wa()
487 intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, in mtl_pipedmc_clock_gating_wa()
753 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, 0, PIPEDMC_ENABLE_MTL(pipe)); in intel_dmc_enable_pipe()
755 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), 0, PIPEDMC_ENABLE); in intel_dmc_enable_pipe()
769 intel_de_rmw(display, MTL_PIPEDMC_CONTROL, PIPEDMC_ENABLE_MTL(pipe), 0); in intel_dmc_disable_pipe()
771 intel_de_rmw(display, PIPEDMC_CONTROL(pipe), PIPEDMC_ENABLE, 0); in intel_dmc_disable_pipe()
818 intel_de_rmw(display, PIPEDMC_BLOCK_PKGC_SW(pipe), in intel_dmc_block_pkgc()
A Dintel_cx0_phy.c96 intel_de_rmw(display, in intel_cx0_program_msgbus_timer()
138 intel_de_rmw(display, in intel_clear_response_ready_flag()
2762 intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port), in intel_program_port_clock_ctl()
2783 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in intel_program_port_clock_ctl()
2820 intel_de_rmw(display, buf_ctl2_reg, in intel_cx0_powerdown_change_sequence()
2835 intel_de_rmw(display, buf_ctl2_reg, in intel_cx0_powerdown_change_sequence()
2853 intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), in intel_cx0_setup_powerdown()
2856 intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port), in intel_cx0_setup_powerdown()
2919 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port), in intel_cx0_phy_lane_reset()
3072 intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), in __intel_cx0pll_enable()
[all …]
A Dintel_pmdemand.c133 intel_de_rmw(display, XELPD_CHICKEN_DCPR_3, 0, DMD_RSP_TIMEOUT_DISABLE); in intel_pmdemand_init()
503 intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(0), in intel_pmdemand_program_dbuf()
506 intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, in intel_pmdemand_program_dbuf()
615 intel_de_rmw(display, XELPDP_INITIATE_PMDEMAND_REQUEST(1), 0, in intel_pmdemand_program_params()
A Dvlv_dsi_pll.c310 intel_de_rmw(display, BXT_DSI_PLL_ENABLE, BXT_DSI_PLL_DO_ENABLE, 0); in bxt_dsi_pll_disable()
558 intel_de_rmw(display, BXT_DSI_PLL_ENABLE, 0, BXT_DSI_PLL_DO_ENABLE); in bxt_dsi_pll_enable()
585 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV1, GLK_TX_ESC_CLK_DIV1_MASK, 0); in bxt_dsi_reset_clocks()
587 intel_de_rmw(display, MIPIO_TXESC_CLK_DIV2, GLK_TX_ESC_CLK_DIV2_MASK, 0); in bxt_dsi_reset_clocks()
A Dintel_dsi_vbt.c343 intel_de_rmw(display, SHOTPLUG_CTL_DDI, in icl_native_gpio_set_value()
353 intel_de_rmw(display, PP_CONTROL(display, index), PANEL_POWER_ON, in icl_native_gpio_set_value()
360 intel_de_rmw(display, PP_CONTROL(display, index), EDP_BLC_ENABLE, in icl_native_gpio_set_value()
367 intel_de_rmw(display, GPIO(display, index), in icl_native_gpio_set_value()
376 intel_de_rmw(display, GPIO(display, index), in icl_native_gpio_set_value()
A Dintel_dvo.c196 intel_de_rmw(display, DVO(port), DVO_ENABLE, 0); in intel_disable_dvo()
213 intel_de_rmw(display, DVO(port), 0, DVO_ENABLE); in intel_enable_dvo()
461 dpll[pipe] = intel_de_rmw(display, DPLL(display, pipe), 0, in intel_dvo_init_dev()
A Dg4x_hdmi.c248 intel_de_rmw(display, hdmi->hdmi_reg, 0, HDMI_AUDIO_ENABLE); in g4x_hdmi_audio_enable()
266 intel_de_rmw(display, hdmi->hdmi_reg, HDMI_AUDIO_ENABLE, 0); in g4x_hdmi_audio_disable()
349 intel_de_rmw(display, TRANS_CHICKEN1(pipe), in cpt_enable_hdmi()
366 intel_de_rmw(display, TRANS_CHICKEN1(pipe), in cpt_enable_hdmi()
A Dintel_backlight.c364 intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0); in lpt_disable_backlight()
374 intel_de_rmw(display, BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE, 0); in pch_disable_backlight()
376 intel_de_rmw(display, BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE, 0); in pch_disable_backlight()
391 intel_de_rmw(display, BLC_PWM_CTL2, BLM_PWM_ENABLE, 0); in i965_disable_backlight()
402 intel_de_rmw(display, VLV_BLC_PWM_CTL2(pipe), BLM_PWM_ENABLE, 0); in vlv_disable_backlight()
413 intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller), in bxt_disable_backlight()
417 intel_de_rmw(display, UTIL_PIN_CTL, UTIL_PIN_ENABLE, 0); in bxt_disable_backlight()
428 intel_de_rmw(display, BXT_BLC_PWM_CTL(panel->backlight.controller), in cnp_disable_backlight()
492 intel_de_rmw(display, SOUTH_CHICKEN2, LPT_PWM_GRANULARITY, in lpt_enable_backlight()
496 intel_de_rmw(display, SOUTH_CHICKEN1, SPT_PWM_GRANULARITY, in lpt_enable_backlight()
A Dintel_lvds.c326 intel_de_rmw(display, lvds_encoder->reg, 0, LVDS_PORT_EN); in intel_enable_lvds()
328 intel_de_rmw(display, PP_CONTROL(display, 0), 0, PANEL_POWER_ON); in intel_enable_lvds()
346 intel_de_rmw(display, PP_CONTROL(display, 0), PANEL_POWER_ON, 0); in intel_disable_lvds()
351 intel_de_rmw(display, lvds_encoder->reg, LVDS_PORT_EN, 0); in intel_disable_lvds()

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