| /drivers/gpu/drm/i915/display/ |
| A D | vlv_dsi.c | 97 if (intel_de_wait_for_set(display, MIPI_GEN_FIFO_STAT(display, port), in vlv_dsi_wait_for_fifo_empty()
191 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), in intel_dsi_host_transfer()
249 if (intel_de_wait_for_set(display, MIPI_INTR_STAT(display, port), mask, 100)) in dpi_send_cmd()
355 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), in glk_dsi_enable_io()
377 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), in glk_dsi_device_ready()
416 if (intel_de_wait_for_set(display, MIPI_CTRL(display, port), in glk_dsi_device_ready()
424 if (intel_de_wait_for_set(display, BXT_MIPI_PORT_CTRL(port), in glk_dsi_device_ready()
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| A D | intel_de.h | 178 intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg, in intel_de_wait_for_set() function
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| A D | intel_pch_display.c | 308 if (intel_de_wait_for_set(display, reg, TRANS_STATE_ENABLE, 100)) in ilk_enable_pch_transcoder()
575 if (intel_de_wait_for_set(display, LPT_TRANSCONF, in lpt_enable_pch_transcoder()
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| A D | hsw_ips.c | 59 if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50)) in hsw_ips_enable()
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| A D | intel_display_power_well.c | 292 if (intel_de_wait_for_set(display, regs->driver, in hsw_wait_for_power_well_enable()
358 intel_de_wait_for_set(display, SKL_FUSE_STATUS, in gen9_wait_for_power_well_fuses()
1472 if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS, in chv_dpio_cmn_power_well_enable()
1892 if (intel_de_wait_for_set(display, XE2LPD_PICA_PW_CTL, in xe2lpd_pica_power_well_enable()
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| A D | intel_hdcp.c | 433 if (intel_de_wait_for_set(display, HDCP_REP_CTL, HDCP_SHA1_READY, 1)) { in intel_write_sha_text()
712 if (intel_de_wait_for_set(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
860 if (intel_de_wait_for_set(display, in intel_hdcp_auth()
955 if (intel_de_wait_for_set(display, in intel_hdcp_auth()
1942 ret = intel_de_wait_for_set(display, in hdcp2_enable_encryption()
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| A D | vlv_dsi_pll.c | 561 if (intel_de_wait_for_set(display, BXT_DSI_PLL_ENABLE, in bxt_dsi_pll_enable()
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| A D | intel_cdclk.c | 1114 if (intel_de_wait_for_set(display, LCPLL1_CTL, LCPLL_PLL_LOCK, 5)) in skl_dpll0_enable()
1817 if (intel_de_wait_for_set(display, in bxt_de_pll_enable()
1848 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1)) in icl_cdclk_pll_enable()
1868 if (intel_de_wait_for_set(display, BXT_DE_PLL_ENABLE, in adlp_cdclk_pll_crawl()
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| A D | intel_lvds.c | 331 if (intel_de_wait_for_set(display, PP_STATUS(display, 0), PP_ON, 5000)) in intel_enable_lvds()
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| A D | intel_ddi.c | 211 if (intel_de_wait_for_set(display, intel_ddi_buf_status_reg(display, port), in intel_wait_ddi_buf_idle()
2301 if (intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), in intel_ddi_wait_for_act_sent()
2387 ret = intel_de_wait_for_set(display, dp_tp_status_reg(encoder, crtc_state), in intel_ddi_wait_for_fec_status()
3862 if (intel_de_wait_for_set(display, in intel_ddi_set_idle_link_train()
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| A D | intel_dpll.c | 1993 if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1)) in _vlv_enable_pll()
2139 if (intel_de_wait_for_set(display, DPLL(display, pipe), DPLL_LOCK_VLV, 1)) in _chv_enable_pll()
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| A D | intel_dpio_phy.c | 393 if (intel_de_wait_for_set(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10)) in bxt_phy_wait_grc_done()
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| A D | intel_dpll_mgr.c | 1398 if (intel_de_wait_for_set(display, DPLL_STATUS, DPLL_LOCK(id), 5)) in skl_ddi_pll_enable()
3916 if (intel_de_wait_for_set(display, enable_reg, PLL_POWER_STATE, 1)) in icl_pll_power_enable()
3928 if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 1)) in icl_pll_enable()
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| A D | icl_dsi.c | 1031 if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans), in gen11_dsi_enable_transcoder()
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| A D | intel_snps_phy.c | 1866 if (intel_de_wait_for_set(display, enable_reg, PLL_LOCK, 5)) in intel_mpllb_enable()
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| A D | intel_display_power.c | 1355 if (intel_de_wait_for_set(display, LCPLL_CTL, LCPLL_PLL_LOCK, 5)) in hsw_restore_lcpll()
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