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Searched refs:intel_de_write (Results 1 – 25 of 60) sorted by relevance

123

/drivers/gpu/drm/i915/display/
A Dintel_vdsc.c597 intel_de_write(display, in intel_dsc_pps_configure()
600 intel_de_write(display, in intel_dsc_pps_configure()
603 intel_de_write(display, in intel_dsc_pps_configure()
606 intel_de_write(display, in intel_dsc_pps_configure()
642 intel_de_write(display, in intel_dsc_pps_configure()
647 intel_de_write(display, in intel_dsc_pps_configure()
652 intel_de_write(display, in intel_dsc_pps_configure()
664 intel_de_write(display, in intel_dsc_pps_configure()
669 intel_de_write(display, in intel_dsc_pps_configure()
674 intel_de_write(display, in intel_dsc_pps_configure()
[all …]
A Dintel_fdi.c483 intel_de_write(display, reg, temp); in intel_fdi_normal_train()
530 intel_de_write(display, reg, temp); in ilk_fdi_link_train()
586 intel_de_write(display, reg, in ilk_fdi_link_train()
628 intel_de_write(display, reg, temp); in gen6_fdi_link_train()
673 intel_de_write(display, reg, in gen6_fdi_link_train()
697 intel_de_write(display, reg, temp); in gen6_fdi_link_train()
708 intel_de_write(display, reg, temp); in gen6_fdi_link_train()
724 intel_de_write(display, reg, in gen6_fdi_link_train()
765 intel_de_write(display, reg, temp); in ivb_manual_fdi_link_train()
819 intel_de_write(display, reg, in ivb_manual_fdi_link_train()
[all …]
A Dvlv_dsi.c114 intel_de_write(display, reg, val); in write_data()
175 intel_de_write(display, MIPI_INTR_STAT(display, port), in intel_dsi_host_transfer()
185 intel_de_write(display, ctrl_reg, in intel_dsi_host_transfer()
658 intel_de_write(display, port_ctrl, temp | DPI_ENABLE); in intel_dsi_port_enable()
800 intel_de_write(display, in intel_dsi_pre_enable()
909 intel_de_write(display, BXT_P_DSI_REGULATOR_TX_CTRL, in intel_dsi_post_disable()
1260 intel_de_write(display, BXT_MIPI_TRANS_HACTIVE(port), in set_dsi_timings()
1264 intel_de_write(display, BXT_MIPI_TRANS_VTOTAL(port), in set_dsi_timings()
1333 intel_de_write(display, MIPI_CTRL(display, PORT_A), in intel_dsi_prepare()
1339 intel_de_write(display, MIPI_CTRL(display, port), in intel_dsi_prepare()
[all …]
A Dintel_vrr.c299 intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), in intel_vrr_set_fixed_rr_timings()
301 intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), in intel_vrr_set_fixed_rr_timings()
474 intel_de_write(display, in intel_vrr_set_transcoder_timings()
493 intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), in intel_vrr_set_transcoder_timings()
497 intel_de_write(display, in intel_vrr_set_transcoder_timings()
593 intel_de_write(display, in intel_vrr_set_db_point_and_transmission_line()
606 intel_de_write(display, TRANS_VRR_VMIN(display, cpu_transcoder), in intel_vrr_enable()
608 intel_de_write(display, TRANS_VRR_VMAX(display, cpu_transcoder), in intel_vrr_enable()
613 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), in intel_vrr_enable()
667 intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), in intel_vrr_transcoder_enable()
[all …]
A Dintel_flipq.c185 intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(crtc->pipe), in intel_flipq_write_tail()
259 intel_de_write(display, PIPEDMC_FQ_CTRL(pipe), 0); in intel_flipq_reset()
261 intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(pipe), 0); in intel_flipq_reset()
262 intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(pipe), 0); in intel_flipq_reset()
267 intel_de_write(display, PIPEDMC_FPQ_HP(pipe, flipq_id), 0); in intel_flipq_reset()
268 intel_de_write(display, PIPEDMC_FPQ_CHP(pipe, flipq_id), 0); in intel_flipq_reset()
273 intel_de_write(display, PIPEDMC_FPQ_ATOMIC_TP(pipe), 0); in intel_flipq_reset()
302 intel_de_write(display, PIPEDMC_SCANLINECMPUPPER(crtc->pipe), in intel_flipq_enable()
304 intel_de_write(display, PIPEDMC_SCANLINECMPLOWER(crtc->pipe), in intel_flipq_enable()
320 intel_de_write(display, PIPEDMC_FQ_CTRL(crtc->pipe), 0); in intel_flipq_disable()
[all …]
A Di9xx_display_sr.c47 intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]); in i9xx_display_restore_swf()
48 intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); in i9xx_display_restore_swf()
51 intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]); in i9xx_display_restore_swf()
54 intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); in i9xx_display_restore_swf()
57 intel_de_write(display, SWF0(display, i), display->restore.saveSWF0[i]); in i9xx_display_restore_swf()
58 intel_de_write(display, SWF1(display, i), display->restore.saveSWF1[i]); in i9xx_display_restore_swf()
61 intel_de_write(display, SWF3(display, i), display->restore.saveSWF3[i]); in i9xx_display_restore_swf()
96 intel_de_write(display, DSPARB(display), display->restore.saveDSPARB); in i9xx_display_sr_restore()
A Dintel_tv.c1418 intel_de_write(display, TV_CSC_Y, in set_color_conversion()
1420 intel_de_write(display, TV_CSC_Y2, in set_color_conversion()
1422 intel_de_write(display, TV_CSC_U, in set_color_conversion()
1424 intel_de_write(display, TV_CSC_U2, in set_color_conversion()
1426 intel_de_write(display, TV_CSC_V, in set_color_conversion()
1428 intel_de_write(display, TV_CSC_V2, in set_color_conversion()
1541 intel_de_write(display, TV_CLR_LEVEL, in intel_tv_pre_enable()
1566 intel_de_write(display, TV_H_LUMA(i), in intel_tv_pre_enable()
1569 intel_de_write(display, TV_H_CHROMA(i), in intel_tv_pre_enable()
1572 intel_de_write(display, TV_V_LUMA(i), in intel_tv_pre_enable()
[all …]
A Dintel_pch_display.c134 intel_de_write(display, hdmi_reg, val); in ibx_sanitize_pch_hdmi_port()
153 intel_de_write(display, dp_reg, val); in ibx_sanitize_pch_dp_port()
229 intel_de_write(display, PCH_TRANS_HTOTAL(pch_transcoder), in ilk_pch_transcoder_set_timings()
233 intel_de_write(display, PCH_TRANS_HSYNC(pch_transcoder), in ilk_pch_transcoder_set_timings()
240 intel_de_write(display, PCH_TRANS_VSYNC(pch_transcoder), in ilk_pch_transcoder_set_timings()
272 intel_de_write(display, reg, val); in ilk_enable_pch_transcoder()
307 intel_de_write(display, reg, val | TRANS_ENABLE); in ilk_enable_pch_transcoder()
390 intel_de_write(display, PCH_DPLL_SEL, temp); in ilk_pch_enable()
441 intel_de_write(display, reg, temp); in ilk_pch_enable()
563 intel_de_write(display, TRANS_CHICKEN2(PIPE_A), val); in lpt_enable_pch_transcoder()
[all …]
A Dintel_display_irq.c264 intel_de_write(display, SDEIMR, sdeimr); in ibx_display_interrupt_update()
505 intel_de_write(display, in i9xx_pipestat_irq_reset()
919 intel_de_write(display, SDEIIR, pch_iir); in ilk_display_irq_handler()
1551 intel_de_write(display, SCPD0, in i915gm_irq_cstate_wa_enable()
1560 intel_de_write(display, SCPD0, in i915gm_irq_cstate_wa_disable()
1841 intel_de_write(display, VLV_EIR, *eir); in vlv_display_error_irq_ack()
1850 intel_de_write(display, VLV_EMR, emr); in vlv_display_error_irq_ack()
1944 intel_de_write(display, DPINVGTT, in _vlv_display_irq_postinstall()
1948 intel_de_write(display, DPINVGTT, in _vlv_display_irq_postinstall()
2044 intel_de_write(display, in gen11_display_irq_reset()
[all …]
A Dintel_backlight.c258 intel_de_write(display, BLC_PWM_CTL, tmp | level); in i9xx_set_backlight()
501 intel_de_write(display, BLC_PWM_PCH_CTL2, pch_ctl2); in lpt_enable_backlight()
582 intel_de_write(display, BLC_PWM_CTL, 0); in i9xx_enable_backlight()
595 intel_de_write(display, BLC_PWM_CTL, ctl); in i9xx_enable_backlight()
625 intel_de_write(display, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
633 intel_de_write(display, BLC_PWM_CTL, ctl); in i965_enable_backlight()
640 intel_de_write(display, BLC_PWM_CTL2, ctl2); in i965_enable_backlight()
696 intel_de_write(display, UTIL_PIN_CTL, val); in bxt_enable_backlight()
702 intel_de_write(display, UTIL_PIN_CTL, in bxt_enable_backlight()
1275 intel_de_write(display, BLC_PWM_PCH_CTL1, in lpt_setup_backlight()
[all …]
A Dicl_dsi.c328 intel_de_write(display, dss_ctl1_reg, dss_ctl1); in configure_dual_link_mode()
381 intel_de_write(display, ADL_MIPIO_DW(port, 8), in gen11_dsi_program_esc_clk_div()
619 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); in gen11_dsi_gate_clocks()
635 intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp); in gen11_dsi_ungate_clocks()
673 intel_de_write(display, ICL_DPCLKA_CFGCR0, val); in gen11_dsi_map_pll()
835 intel_de_write(display, in gen11_dsi_configure_transcoder()
952 intel_de_write(display, in gen11_dsi_set_transcoder_timings()
981 intel_de_write(display, in gen11_dsi_set_transcoder_timings()
996 intel_de_write(display, in gen11_dsi_set_transcoder_timings()
1011 intel_de_write(display, in gen11_dsi_set_transcoder_timings()
[all …]
A Dg4x_hdmi.c62 intel_de_write(display, intel_hdmi->hdmi_reg, hdmi_val); in intel_hdmi_prepare()
231 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in g4x_hdmi_enable_port()
294 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
296 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
308 intel_de_write(display, intel_hdmi->hdmi_reg, in ibx_enable_hdmi()
316 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
318 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in ibx_enable_hdmi()
356 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in cpt_enable_hdmi()
363 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in cpt_enable_hdmi()
393 intel_de_write(display, intel_hdmi->hdmi_reg, temp); in intel_disable_hdmi()
[all …]
A Dintel_crt.c219 intel_de_write(display, crt->adpa_reg, adpa); in intel_crt_set_dpms()
498 intel_de_write(display, crt->adpa_reg, adpa); in ilk_crt_detect_hotplug()
508 intel_de_write(display, crt->adpa_reg, save_adpa); in ilk_crt_detect_hotplug()
553 intel_de_write(display, crt->adpa_reg, adpa); in valleyview_crt_detect_hotplug()
559 intel_de_write(display, crt->adpa_reg, save_adpa); in valleyview_crt_detect_hotplug()
617 intel_de_write(display, PORT_HOTPLUG_STAT(display), in intel_crt_detect_hotplug()
759 intel_de_write(display, in intel_crt_load_detect()
793 intel_de_write(display, in intel_crt_load_detect()
972 intel_de_write(display, crt->adpa_reg, adpa); in intel_crt_reset()
1030 intel_de_write(display, adpa_reg, in intel_crt_init()
[all …]
A Dintel_fifo_underrun.c106 intel_de_write(display, reg, enable_mask | PIPE_FIFO_UNDERRUN_STATUS); in i9xx_check_fifo_underruns()
124 intel_de_write(display, reg, in i9xx_set_fifo_underrun_reporting()
157 intel_de_write(display, GEN7_ERR_INT, ERR_INT_FIFO_UNDERRUN(pipe)); in ivb_check_fifo_underruns()
169 intel_de_write(display, GEN7_ERR_INT, in ivb_set_fifo_underrun_reporting()
221 intel_de_write(display, SERR_INT, in cpt_check_pch_fifo_underruns()
235 intel_de_write(display, SERR_INT, in cpt_set_fifo_underrun_reporting()
A Dintel_fbc.c328 intel_de_write(display, FBC_CONTROL, fbc_ctl); in i8xx_fbc_deactivate()
346 intel_de_write(display, FBC_TAG(i), 0); in i8xx_fbc_activate()
349 intel_de_write(display, FBC_CONTROL2, in i8xx_fbc_activate()
351 intel_de_write(display, FBC_FENCE_OFF, in i8xx_fbc_activate()
355 intel_de_write(display, FBC_CONTROL, in i8xx_fbc_activate()
393 intel_de_write(display, FBC_CFB_BASE, in i8xx_fbc_program_cfb()
395 intel_de_write(display, FBC_LL_BASE, in i8xx_fbc_program_cfb()
469 intel_de_write(display, DPFC_FENCE_YOFF, in g4x_fbc_activate()
472 intel_de_write(display, DPFC_CONTROL, in g4x_fbc_activate()
503 intel_de_write(display, DPFC_CB_BASE, in g4x_fbc_program_cfb()
[all …]
A Dintel_dp_test.c235 intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0); in intel_dp_phy_pattern_update()
243 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
249 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
255 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
267 intel_de_write(display, DDI_DP_COMP_PAT(pipe, 0), pattern_val); in intel_dp_phy_pattern_update()
269 intel_de_write(display, DDI_DP_COMP_PAT(pipe, 1), pattern_val); in intel_dp_phy_pattern_update()
271 intel_de_write(display, DDI_DP_COMP_PAT(pipe, 2), pattern_val); in intel_dp_phy_pattern_update()
272 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
285 intel_de_write(display, DDI_DP_COMP_CTL(pipe), in intel_dp_phy_pattern_update()
297 intel_de_write(display, DDI_DP_COMP_CTL(pipe), 0x0); in intel_dp_phy_pattern_update()
A Dintel_hdmi.c298 intel_de_write(display, reg, val); in ibx_write_infoframe()
313 intel_de_write(display, reg, val); in ibx_write_infoframe()
376 intel_de_write(display, reg, val); in cpt_write_infoframe()
391 intel_de_write(display, reg, val); in cpt_write_infoframe()
447 intel_de_write(display, reg, val); in vlv_write_infoframe()
450 intel_de_write(display, in vlv_write_infoframe()
456 intel_de_write(display, in vlv_write_infoframe()
463 intel_de_write(display, reg, val); in vlv_write_infoframe()
524 intel_de_write(display, in hsw_write_infoframe()
531 intel_de_write(display, in hsw_write_infoframe()
[all …]
A Dg4x_dp.c215 intel_de_write(display, DP_A, intel_dp->DP); in ilk_edp_pll_on()
230 intel_de_write(display, DP_A, intel_dp->DP); in ilk_edp_pll_on()
248 intel_de_write(display, DP_A, intel_dp->DP); in ilk_edp_pll_off()
435 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
439 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
459 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in intel_dp_link_down()
489 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in g4x_dp_audio_enable()
508 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in g4x_dp_audio_disable()
610 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in cpt_set_link_train()
638 intel_de_write(display, intel_dp->output_reg, intel_dp->DP); in g4x_set_link_train()
[all …]
A Dintel_hdcp.c568 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
577 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
585 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
594 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
605 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
613 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
622 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
631 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
710 intel_de_write(display, HDCP_REP_CTL, in intel_hdcp_validate_v_prime()
853 intel_de_write(display, in intel_hdcp_auth()
[all …]
A Dintel_combo_phy.c90 intel_de_write(display, ICL_PORT_COMP_DW9(phy), procmon->dw9); in icl_set_procmon_ref_values()
91 intel_de_write(display, ICL_PORT_COMP_DW10(phy), procmon->dw10); in icl_set_procmon_ref_values()
347 intel_de_write(display, ICL_PHY_MISC(phy), val); in icl_combo_phys_init()
355 intel_de_write(display, ICL_PORT_TX_DW8_GRP(phy), val); in icl_combo_phys_init()
360 intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), val); in icl_combo_phys_init()
A Dvlv_dsi_pll.c376 intel_de_write(display, MIPI_CTRL(display, port), in vlv_dsi_reset_clocks()
419 intel_de_write(display, MIPIO_TXESC_CLK_DIV1, in glk_dsi_program_esc_clock()
421 intel_de_write(display, MIPIO_TXESC_CLK_DIV2, in glk_dsi_program_esc_clock()
475 intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_program_clocks()
546 intel_de_write(display, BXT_DSI_PLL_CTL, config->dsi_pll.ctrl); in bxt_dsi_pll_enable()
583 intel_de_write(display, BXT_MIPI_CLOCK_CTL, tmp); in bxt_dsi_reset_clocks()
589 intel_de_write(display, MIPI_EOT_DISABLE(display, port), CLOCKSTOP); in bxt_dsi_reset_clocks()
A Di9xx_wm.c188 intel_de_write(display, INSTPM, val); in _intel_set_memory_cxsr()
848 intel_de_write(display, DSPHOWM, 0); in vlv_write_wm_values()
850 intel_de_write(display, DSPFW4, 0); in vlv_write_wm_values()
851 intel_de_write(display, DSPFW5, 0); in vlv_write_wm_values()
852 intel_de_write(display, DSPFW6, 0); in vlv_write_wm_values()
867 intel_de_write(display, DSPFW7_CHV, in vlv_write_wm_values()
870 intel_de_write(display, DSPFW8_CHV, in vlv_write_wm_values()
873 intel_de_write(display, DSPFW9_CHV, in vlv_write_wm_values()
876 intel_de_write(display, DSPHOWM, in vlv_write_wm_values()
888 intel_de_write(display, DSPFW7, in vlv_write_wm_values()
[all …]
A Dintel_pps.c773 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_vdd_on_unlocked()
844 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_vdd_off_sync_unlocked()
985 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1001 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1013 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_on_unlocked()
1060 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_off_unlocked()
1106 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_backlight_on()
1127 intel_de_write(display, pp_ctrl_reg, pp); in intel_pps_backlight_off()
1188 intel_de_write(display, pp_on_reg, 0); in vlv_detach_power_sequencer()
1626 intel_de_write(display, regs.pp_ctrl, pp); in pps_init_registers()
[all …]
A Dintel_display_power_well.c677 intel_de_write(display, DC_STATE_EN, state); in gen9_write_dc_state()
688 intel_de_write(display, DC_STATE_EN, state); in gen9_write_dc_state()
1217 intel_de_write(display, MI_ARB_VLV, in vlv_init_display_clock_gating()
1219 intel_de_write(display, CBR1_VLV, 0); in vlv_init_display_clock_gating()
1222 intel_de_write(display, RAWCLK_FREQ_VLV, in vlv_init_display_clock_gating()
1503 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_dpio_cmn_power_well_enable()
1533 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_dpio_cmn_power_well_disable()
1630 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_phy_powergate_ch()
1663 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_phy_powergate_lanes()
1745 intel_de_write(display, DISPLAY_PHY_CONTROL, in chv_pipe_power_well_sync_hw()
[all …]
A Dintel_pch_refclk.c114 intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_GATE); in lpt_disable_iclkip()
230 intel_de_write(display, PIXCLK_GATE, PIXCLK_GATE_UNGATE); in lpt_program_iclkip()
618 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
637 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
648 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()
662 intel_de_write(display, PCH_DREF_CONTROL, val); in ilk_init_pch_refclk()

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