Searched refs:intel_dkl_phy_write (Results 1 – 4 of 4) sorted by relevance
| /drivers/gpu/drm/i915/display/ |
| A D | intel_dkl_phy.h | 19 intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val);
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| A D | intel_dkl_phy.c | 70 intel_dkl_phy_write(struct intel_display *display, struct intel_dkl_phy_reg reg, u32 val) in intel_dkl_phy_write() function
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| A D | intel_dpll_mgr.c | 3856 intel_dkl_phy_write(display, DKL_REFCLKIN_CTL(tc_port), val); in dkl_pll_write()
3861 intel_dkl_phy_write(display, DKL_CLKTOP2_CORECLKCTL1(tc_port), val); in dkl_pll_write()
3869 intel_dkl_phy_write(display, DKL_CLKTOP2_HSCLKCTL(tc_port), val); in dkl_pll_write()
3881 intel_dkl_phy_write(display, DKL_PLL_DIV1(tc_port), val); in dkl_pll_write()
3889 intel_dkl_phy_write(display, DKL_PLL_SSC(tc_port), val); in dkl_pll_write()
3895 intel_dkl_phy_write(display, DKL_PLL_BIAS(tc_port), val); in dkl_pll_write()
3901 intel_dkl_phy_write(display, DKL_PLL_TDC_COLDST_BIAS(tc_port), val); in dkl_pll_write()
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| A D | intel_ddi.c | 1414 intel_dkl_phy_write(display, DKL_TX_PMD_LANE_SUS(tc_port, ln), 0); in tgl_dkl_phy_set_signal_levels()
2158 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); in tgl_dkl_phy_check_and_rewrite()
2160 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); in tgl_dkl_phy_check_and_rewrite()
2242 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 0), ln0); in icl_program_mg_dp_mode()
2243 intel_dkl_phy_write(display, DKL_DP_MODE(tc_port, 1), ln1); in icl_program_mg_dp_mode()
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