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Searched refs:intel_engine_mask_t (Results 1 – 25 of 38) sorted by relevance

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/drivers/gpu/drm/i915/gt/
A Dintel_reset.c188 intel_engine_mask_t engine_mask, in g33_do_reset()
198 intel_engine_mask_t engine_mask, in g4x_do_reset()
331 intel_engine_mask_t tmp; in __gen6_reset_engines()
527 intel_engine_mask_t tmp; in __gen11_reset_engines()
617 intel_engine_mask_t tmp; in gen8_reset_engines()
667 intel_engine_mask_t mask, in mock_reset()
718 static intel_engine_mask_t
879 intel_engine_mask_t awake = 0; in reset_prepare()
973 intel_engine_mask_t awake; in __intel_gt_set_wedged()
1209 intel_engine_mask_t awake; in intel_gt_reset()
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A Dintel_engine_types.h59 typedef u32 intel_engine_mask_t; typedef
60 #define ALL_ENGINES ((intel_engine_mask_t)~0ul)
61 #define VIRTUAL_ENGINES BIT(BITS_PER_TYPE(intel_engine_mask_t) - 1)
376 intel_engine_mask_t mask;
384 intel_engine_mask_t logical_mask;
443 intel_engine_mask_t saturated; /* submitting semaphores too late? */
A Dintel_gt_types.h215 intel_engine_mask_t cslices;
262 intel_engine_mask_t engine_mask;
308 intel_engine_mask_t engine_mask;
A Dintel_reset.h26 intel_engine_mask_t engine_mask,
34 intel_engine_mask_t stalled_mask,
A Dintel_engine_pm.h44 intel_engine_mask_t tmp, mask = engine->mask; in intel_engine_pm_might_get()
80 intel_engine_mask_t tmp, mask = engine->mask; in intel_engine_pm_might_put()
A Dintel_breadcrumbs_types.h50 intel_engine_mask_t engine_mask;
A Dselftest_reset.c19 intel_engine_mask_t mask, in __igt_reset_stolen()
277 intel_engine_mask_t awake; in igt_atomic_reset()
A Dintel_tlb.c54 intel_engine_mask_t awake, tmp; in mmio_invalidate_full()
A Dintel_gt.h150 intel_engine_mask_t engine_mask);
/drivers/gpu/drm/i915/gvt/
A Dscheduler.h148 intel_engine_mask_t engine_mask);
153 intel_engine_mask_t engine_mask,
167 intel_engine_mask_t engine_mask);
A Dexeclist.c523 intel_engine_mask_t engine_mask) in clean_execlist()
527 intel_engine_mask_t tmp; in clean_execlist()
537 intel_engine_mask_t engine_mask) in reset_execlist()
540 intel_engine_mask_t tmp; in reset_execlist()
547 intel_engine_mask_t engine_mask) in init_execlist()
A Dgvt.h145 int (*init)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
146 void (*clean)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
147 void (*reset)(struct intel_vgpu *vgpu, intel_engine_mask_t engine_mask);
502 intel_engine_mask_t engine_mask);
A Dvgpu.c436 intel_engine_mask_t engine_mask) in intel_gvt_reset_vgpu_locked()
440 intel_engine_mask_t resetting_eng = dmlr ? ALL_ENGINES : engine_mask; in intel_gvt_reset_vgpu_locked()
A Dscheduler.c1049 intel_engine_mask_t engine_mask) in intel_vgpu_clean_workloads()
1054 intel_engine_mask_t tmp; in intel_vgpu_clean_workloads()
1344 intel_engine_mask_t engine_mask) in intel_vgpu_reset_submission()
1468 intel_engine_mask_t engine_mask, in intel_vgpu_select_submission_ops()
/drivers/gpu/drm/i915/
A Di915_gpu_error.h266 intel_engine_mask_t engine_mask);
269 intel_engine_mask_t engine_mask) in intel_klog_error_capture()
280 intel_engine_mask_t engine_mask, u32 dump_flags);
342 i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) in i915_capture_error_state()
A Di915_scheduler_types.h69 intel_engine_mask_t semaphores;
A Dintel_device_info.h233 intel_engine_mask_t platform_engine_mask; /* Engines supported by the HW */
A Di915_request.h271 intel_engine_mask_t execution_mask;
A Di915_gpu_error.c1675 intel_engine_mask_t engine_mask, in gt_record_engines()
2067 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) in __i915_gpu_coredump()
2118 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags) in i915_gpu_coredump()
2165 intel_engine_mask_t engine_mask, u32 dump_flags) in i915_capture_error_state()
2217 intel_engine_mask_t engine_mask) in intel_klog_error_capture()
A Dintel_device_info.c393 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); in intel_device_info_runtime_init()
/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc.h159 intel_engine_mask_t reset_fail_mask;
536 void intel_guc_submission_reset(struct intel_guc *guc, intel_engine_mask_t stalled);
A Dintel_uc.h49 void intel_uc_reset(struct intel_uc *uc, intel_engine_mask_t stalled);
A Dintel_guc_submission.c1756 intel_engine_mask_t tmp, mask = ve->mask; in guc_virtual_get_sibling()
4002 intel_engine_mask_t tmp, mask = ce->engine->mask; in guc_virtual_context_pin()
4013 intel_engine_mask_t tmp, mask = ce->engine->mask; in guc_virtual_context_unpin()
4029 intel_engine_mask_t tmp, mask = ce->engine->mask; in guc_virtual_context_enter()
4040 intel_engine_mask_t tmp, mask = ce->engine->mask; in guc_virtual_context_exit()
4281 intel_engine_mask_t tmp, mask = b->engine_mask; in guc_irq_enable_breadcrumbs()
4294 intel_engine_mask_t tmp, mask = b->engine_mask; in guc_irq_disable_breadcrumbs()
4532 intel_engine_mask_t tmp, mask = engine->mask; in virtual_guc_bump_serial()
5188 intel_engine_mask_t engine_mask; in capture_error_state()
5319 intel_engine_mask_t reset_fail_mask; in reset_fail_worker_func()
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A Dintel_gsc_uc.c100 intel_engine_mask_t mask; in gsc_engine_supported()
A Dintel_huc.c257 intel_engine_mask_t mask = gt->info.engine_mask; in vcs_supported()

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