Searched refs:intel_pcode_write (Results 1 – 8 of 8) sorted by relevance
| /drivers/gpu/drm/i915/display/ |
| A D | hsw_ips.c | 42 intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL, in hsw_ips_enable()
75 intel_pcode_write(display->drm, DISPLAY_IPS_CONTROL, 0)); in hsw_ips_disable()
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| A D | intel_cdclk.c | 892 ret = intel_pcode_write(display->drm, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0); in bdw_set_cdclk()
920 intel_pcode_write(display->drm, HSW_PCODE_DE_WRITE_FREQ_REQ, in bdw_set_cdclk()
1223 intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, in skl_set_cdclk()
2213 ret = intel_pcode_write(display->drm, SKL_PCODE_CDCLK_CONTROL, in bxt_set_cdclk()
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| A D | intel_display_power_well.c | 506 ret = intel_pcode_write(display->drm, ICL_PCODE_EXIT_TCCOLD, 0); in icl_tc_cold_exit()
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| A D | intel_display_power.c | 1261 if (intel_pcode_write(display->drm, GEN6_PCODE_WRITE_D_COMP, val)) in hsw_write_dcomp()
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| A D | intel_hdcp.c | 403 ret = intel_pcode_write(display->drm, SKL_PCODE_LOAD_HDCP_KEYS, 1); in intel_hdcp_load_keys()
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| A D | skl_watermark.c | 185 ret = intel_pcode_write(display->drm, GEN9_PCODE_SAGV_CONTROL, in skl_sagv_enable()
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| /drivers/gpu/drm/i915/ |
| A D | intel_pcode.h | 33 #define intel_pcode_write(drm, mbox, val) \ macro
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| /drivers/gpu/drm/xe/ |
| A D | xe_pcode.h | 40 #define intel_pcode_write(drm, mbox, val) \ macro
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