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Searched refs:intel_uncore_read (Results 1 – 25 of 50) sorted by relevance

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/drivers/gpu/drm/i915/
A Dvlv_suspend.c121 s->arb_mode = intel_uncore_read(uncore, ARB_MODE); in vlv_save_gunit_s0ix_state()
132 s->ecochk = intel_uncore_read(uncore, GAM_ECOCHK); in vlv_save_gunit_s0ix_state()
139 s->g3dctl = intel_uncore_read(uncore, VLV_G3DCTL); in vlv_save_gunit_s0ix_state()
141 s->mbctl = intel_uncore_read(uncore, GEN6_MBCTL); in vlv_save_gunit_s0ix_state()
155 s->ecobus = intel_uncore_read(uncore, ECOBUS); in vlv_save_gunit_s0ix_state()
164 s->gt_imr = intel_uncore_read(uncore, GTIMR); in vlv_save_gunit_s0ix_state()
165 s->gt_ier = intel_uncore_read(uncore, GTIER); in vlv_save_gunit_s0ix_state()
166 s->pm_imr = intel_uncore_read(uncore, GEN6_PMIMR); in vlv_save_gunit_s0ix_state()
167 s->pm_ier = intel_uncore_read(uncore, GEN6_PMIER); in vlv_save_gunit_s0ix_state()
173 s->tilectl = intel_uncore_read(uncore, TILECTL); in vlv_save_gunit_s0ix_state()
[all …]
A Dintel_clock_gating.c91 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
119 intel_uncore_read(&i915->uncore, GEN9_CLKGATE_DIS_0) | in glk_init_clock_gating()
174 (intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | in ilk_init_clock_gating()
178 (intel_uncore_read(&i915->uncore, DISP_ARB_CTL) | in ilk_init_clock_gating()
222 val = intel_uncore_read(&i915->uncore, TRANS_CHICKEN2(pipe)); in cpt_init_clock_gating()
242 tmp = intel_uncore_read(&i915->uncore, MCH_SSKPD); in gen6_check_mch_setup()
258 intel_uncore_read(&i915->uncore, GEN6_UCGCTL1) | in gen6_init_clock_gating()
291 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN1) | in gen6_init_clock_gating()
294 intel_uncore_read(&i915->uncore, ILK_DISPLAY_CHICKEN2) | in gen6_init_clock_gating()
297 intel_uncore_read(&i915->uncore, ILK_DSPCLK_GATE_D) | in gen6_init_clock_gating()
[all …]
A Di915_gpu_error.c1212 intel_uncore_read(uncore, FENCE_REG(i)); in gt_record_fences()
1335 intel_uncore_read(engine->uncore, in engine_record_registers()
1339 intel_uncore_read(engine->uncore, in engine_record_registers()
1774 intel_uncore_read(uncore, in gt_record_global_nonguc_regs()
1781 intel_uncore_read(uncore, in gt_record_global_nonguc_regs()
1784 intel_uncore_read(uncore, in gt_record_global_nonguc_regs()
1787 intel_uncore_read(uncore, in gt_record_global_nonguc_regs()
1803 gt->eir = intel_uncore_read(uncore, EIR); in gt_record_global_nonguc_regs()
1839 gt->fault_data0 = intel_uncore_read(uncore, in gt_record_global_regs()
1841 gt->fault_data1 = intel_uncore_read(uncore, in gt_record_global_regs()
[all …]
A Di915_debugfs.c342 intel_uncore_read(uncore, DCC)); in i915_swizzle_info()
344 intel_uncore_read(uncore, DCC2)); in i915_swizzle_info()
351 intel_uncore_read(uncore, MAD_DIMM_C0)); in i915_swizzle_info()
353 intel_uncore_read(uncore, MAD_DIMM_C1)); in i915_swizzle_info()
355 intel_uncore_read(uncore, MAD_DIMM_C2)); in i915_swizzle_info()
357 intel_uncore_read(uncore, TILECTL)); in i915_swizzle_info()
360 intel_uncore_read(uncore, GAMTARBMODE)); in i915_swizzle_info()
363 intel_uncore_read(uncore, ARB_MODE)); in i915_swizzle_info()
365 intel_uncore_read(uncore, DISP_ARB_CTL)); in i915_swizzle_info()
A Di915_irq.c100 u32 val = intel_uncore_read(uncore, reg); in gen2_assert_iir_is_zero()
192 error_status = intel_uncore_read(&dev_priv->uncore, reg); in ivb_parity_work()
250 gt_iir = intel_uncore_read(&dev_priv->uncore, GTIIR); in valleyview_irq_handler()
252 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in valleyview_irq_handler()
345 iir = intel_uncore_read(&dev_priv->uncore, VLV_IIR); in cherryview_irq_handler()
861 *eir = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
864 *eir_stuck = intel_uncore_read(&dev_priv->uncore, EIR); in i9xx_error_irq_ack()
878 emr = intel_uncore_read(&dev_priv->uncore, EMR); in i9xx_error_irq_ack()
893 intel_uncore_read(&dev_priv->uncore, PGTBL_ER)); in i9xx_error_irq_handler()
960 iir = intel_uncore_read(&dev_priv->uncore, GEN2_IIR); in i915_irq_handler()
[all …]
A Di915_vgpu.c267 intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.base)); in intel_vgt_balloon()
269 intel_uncore_read(uncore, vgtif_reg(avail_rs.mappable_gmadr.size)); in intel_vgt_balloon()
271 intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.base)); in intel_vgt_balloon()
273 intel_uncore_read(uncore, vgtif_reg(avail_rs.nonmappable_gmadr.size)); in intel_vgt_balloon()
A Di915_hwmon.c108 reg_value = intel_uncore_read(uncore, rgadr); in hwm_field_read_and_scale()
153 reg_val = intel_uncore_read(uncore, rgaddr); in hwm_energy()
178 r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); in hwm_power1_max_interval_show()
337 reg_val = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_temp); in hwm_temp_read()
370 reg_value = intel_uncore_read(ddat->uncore, hwmon->rg.gt_perf_status); in hwm_in_read()
416 r = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); in hwm_power_max_read()
478 nval = intel_uncore_read(ddat->uncore, hwmon->rg.pkg_rapl_limit); in hwm_power_max_write()
683 reg_val = intel_uncore_read(ddat->uncore, hwmon->rg.fan_speed); in hwm_fan_input_read()
874 val_sku_unit = intel_uncore_read(uncore, in hwm_get_preregistration_info()
882 ddat->fi.reg_val_prev = intel_uncore_read(uncore, in hwm_get_preregistration_info()
/drivers/gpu/drm/i915/gt/
A Dintel_sseu_debugfs.c24 sig1[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG1); in cherryview_sseu_device_status()
25 sig1[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG1); in cherryview_sseu_device_status()
26 sig2[0] = intel_uncore_read(uncore, CHV_POWER_SS0_SIG2); in cherryview_sseu_device_status()
27 sig2[1] = intel_uncore_read(uncore, CHV_POWER_SS1_SIG2); in cherryview_sseu_device_status()
65 s_reg[s] = intel_uncore_read(uncore, GEN10_SLICE_PGCTL_ACK(s)) & in gen11_sseu_device_status()
67 eu_reg[2 * s] = intel_uncore_read(uncore, in gen11_sseu_device_status()
69 eu_reg[2 * s + 1] = intel_uncore_read(uncore, in gen11_sseu_device_status()
119 s_reg[s] = intel_uncore_read(uncore, GEN9_SLICE_PGCTL_ACK(s)); in gen9_sseu_device_status()
121 intel_uncore_read(uncore, GEN9_SS01_EU_PGCTL_ACK(s)); in gen9_sseu_device_status()
123 intel_uncore_read(uncore, GEN9_SS23_EU_PGCTL_ACK(s)); in gen9_sseu_device_status()
[all …]
A Dintel_rps.c336 total = intel_uncore_read(uncore, DMIEC); in __ips_chipset_val()
337 total += intel_uncore_read(uncore, DDREC); in __ips_chipset_val()
338 total += intel_uncore_read(uncore, CSIEC); in __ips_chipset_val()
357 tsfs = intel_uncore_read(uncore, TSFS); in ips_mch_val()
404 count = intel_uncore_read(uncore, GFXEC); in __gen5_ips_update()
1116 intel_uncore_read(uncore, MTL_RP_STATE_CAP); in mtl_get_freq_caps()
1118 intel_uncore_read(uncore, MTL_MPE_FREQUENCY) : in mtl_get_freq_caps()
1961 intel_uncore_read(uncore, MEMINTRSTS)); in gen5_rps_irq_handler()
1966 max_avg = intel_uncore_read(uncore, RCBMAXAVG); in gen5_rps_irq_handler()
1967 min_avg = intel_uncore_read(uncore, RCBMINAVG); in gen5_rps_irq_handler()
[all …]
A Dintel_rc6.c289 pcbr = intel_uncore_read(uncore, VLV_PCBR); in chv_rc6_init()
311 pcbr = intel_uncore_read(uncore, VLV_PCBR); in vlv_rc6_init()
433 rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL); in bxt_check_bios_rc6_setup()
434 rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE); in bxt_check_bios_rc6_setup()
453 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK; in bxt_check_bios_rc6_setup()
469 if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) || in bxt_check_bios_rc6_setup()
470 !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) || in bxt_check_bios_rc6_setup()
471 !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) { in bxt_check_bios_rc6_setup()
476 if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) { in bxt_check_bios_rc6_setup()
481 if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) { in bxt_check_bios_rc6_setup()
[all …]
A Dintel_gt_pm_debugfs.c97 pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS); in vlv_drpc()
98 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); in vlv_drpc()
126 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); in gen6_drpc()
129 intel_uncore_read(uncore, GEN9_PG_ENABLE); in gen6_drpc()
131 intel_uncore_read(uncore, GEN9_PWRGT_DOMAIN_STATUS); in gen6_drpc()
211 rgvmodectl = intel_uncore_read(uncore, MEMMODECTL); in ilk_drpc()
212 rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL); in ilk_drpc()
273 rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL); in mtl_drpc()
274 mtl_powergate_enable = intel_uncore_read(uncore, GEN9_PG_ENABLE); in mtl_drpc()
275 mtl_powergate_status = intel_uncore_read(uncore, in mtl_drpc()
[all …]
A Dintel_sseu.c240 intel_uncore_read(uncore, XEHP_EU_ENABLE)); in xehp_sseu_info_init()
274 intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE)); in gen12_sseu_info_init()
281 intel_uncore_read(uncore, GEN11_EU_DISABLE)); in gen12_sseu_info_init()
311 intel_uncore_read(uncore, GEN11_GT_SLICE_ENABLE)); in gen11_sseu_info_init()
317 intel_uncore_read(uncore, GEN11_EU_DISABLE)); in gen11_sseu_info_init()
332 fuse = intel_uncore_read(gt->uncore, CHV_FUSE_GT); in cherryview_sseu_info_init()
384 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); in gen9_sseu_info_init()
488 fuse2 = intel_uncore_read(uncore, GEN8_FUSE2); in bdw_sseu_info_init()
498 eu_disable0 = intel_uncore_read(uncore, GEN8_EU_DISABLE0); in bdw_sseu_info_init()
499 eu_disable1 = intel_uncore_read(uncore, GEN8_EU_DISABLE1); in bdw_sseu_info_init()
[all …]
A Dintel_gt_clock_utils.c16 u32 ts_override = intel_uncore_read(uncore, GEN9_TIMESTAMP_OVERRIDE); in read_reference_ts_freq()
57 u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); in gen11_read_clock_frequency()
72 u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0); in gen11_read_clock_frequency()
89 u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE); in gen9_read_clock_frequency()
A Dselftest_rps.c209 intel_uncore_read(rps_to_uncore(rps), in show_pstate_limits()
214 intel_uncore_read(rps_to_uncore(rps), in show_pstate_limits()
481 u32 throttle = intel_uncore_read(gt->uncore, in live_rps_control()
945 timeout = intel_uncore_read(uncore, GEN6_RP_UP_EI); in __rps_up_interrupt()
964 intel_uncore_read(uncore, GEN6_RP_PREV_UP), in __rps_up_interrupt()
966 intel_uncore_read(uncore, GEN6_RP_UP_EI)); in __rps_up_interrupt()
993 timeout = intel_uncore_read(uncore, GEN6_RP_DOWN_EI); in __rps_down_interrupt()
1009 intel_uncore_read(uncore, GEN6_RP_PREV_DOWN), in __rps_down_interrupt()
1011 intel_uncore_read(uncore, GEN6_RP_DOWN_EI), in __rps_down_interrupt()
1012 intel_uncore_read(uncore, GEN6_RP_PREV_UP), in __rps_down_interrupt()
[all …]
A Dintel_ggtt_fencing.c591 if (intel_uncore_read(uncore, DISP_ARB_CTL) & in detect_bit_6_swizzle()
602 dimm_c0 = intel_uncore_read(uncore, MAD_DIMM_C0); in detect_bit_6_swizzle()
603 dimm_c1 = intel_uncore_read(uncore, MAD_DIMM_C1); in detect_bit_6_swizzle()
669 u32 dcc = intel_uncore_read(uncore, DCC); in detect_bit_6_swizzle()
708 !(intel_uncore_read(uncore, DCC2) & DCC2_MODIFIED_ENHANCED_DISABLE)) { in detect_bit_6_swizzle()
864 num_fences = intel_uncore_read(uncore, in intel_ggtt_init_fences()
A Dintel_wopcm.c203 u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET); in __wopcm_regs_locked()
204 u32 reg_size = intel_uncore_read(uncore, GUC_WOPCM_SIZE); in __wopcm_regs_locked()
220 return intel_uncore_read(uncore, GUC_SHIM_CONTROL2) & GUC_IS_PRIVILEGED; in __wopcm_regs_writable()
A Dintel_engine_cs.c299 cxt_size = intel_uncore_read(uncore, GEN7_CXT_SIZE); in intel_engine_context_size()
303 cxt_size = intel_uncore_read(uncore, CXT_SIZE); in intel_engine_context_size()
318 cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1; in intel_engine_context_size()
776 fuse1 = intel_uncore_read(gt->uncore, HSW_PAVP_FUSE1); in engine_mask_apply_media_fuses()
1784 intel_uncore_read(uncore, RING_INSTDONE(mmio_base)); in intel_engine_get_instdone()
1790 intel_uncore_read(uncore, GEN7_SC_INSTDONE); in intel_engine_get_instdone()
1793 intel_uncore_read(uncore, GEN12_SC_INSTDONE_EXTRA); in intel_engine_get_instdone()
1824 intel_uncore_read(uncore, GEN7_SC_INSTDONE); in intel_engine_get_instdone()
1826 intel_uncore_read(uncore, GEN7_SAMPLER_INSTDONE); in intel_engine_get_instdone()
1828 intel_uncore_read(uncore, GEN7_ROW_INSTDONE); in intel_engine_get_instdone()
[all …]
A Dintel_gt_mcr.c125 intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3)); in intel_gt_mcr_init()
138 intel_uncore_read(gt->uncore, in intel_gt_mcr_init()
142 intel_uncore_read(gt->uncore, XEHP_FUSE4)); in intel_gt_mcr_init()
166 ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) & in intel_gt_mcr_init()
738 return intel_uncore_read(gt->uncore, mcr_reg_cast(reg)); in intel_gt_mcr_read_any()
/drivers/gpu/drm/i915/soc/
A Dintel_dram.c59 return intel_uncore_read(&i915->uncore, CSHRDDR3CTL) & CSHRDDR3CTL_DDR3; in pnv_is_ddr3()
66 tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG); in pnv_mem_freq()
168 fsb = intel_uncore_read(&i915->uncore, CLKCFG) & CLKCFG_FSB_MASK; in i9xx_fsb_freq()
395 val = intel_uncore_read(&i915->uncore, in skl_dram_get_channels_info()
401 val = intel_uncore_read(&i915->uncore, in skl_dram_get_channels_info()
432 val = intel_uncore_read(&i915->uncore, in skl_get_dram_type()
555 val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i)); in bxt_get_dram_info()
669 u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL); in xelpdp_get_dram_info()
A Dintel_rom.c34 return intel_uncore_read(rom->uncore, PRIMARY_SPI_TRIGGER); in spi_read32()
53 static_region = intel_uncore_read(rom->uncore, SPI_STATIC_REGIONS); in intel_rom_spi()
57 rom->offset = intel_uncore_read(rom->uncore, OROM_OFFSET) & OROM_OFFSET_MASK; in intel_rom_spi()
/drivers/gpu/drm/i915/gt/uc/
A Dintel_guc_fw.c99 u32 val = intel_uncore_read(uncore, GUC_STATUS); in guc_load_done()
218 intel_uncore_read(uncore, GUC_HEADER_INFO)); in guc_wait_ucode()
236 intel_uncore_read(uncore, SOFT_SCRATCH(13))); in guc_wait_ucode()
265 intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt))); in guc_wait_ucode()
A Dintel_uc.c73 guc_status = intel_uncore_read(gt->uncore, GUC_STATUS); in __intel_uc_reset_hw()
194 val = intel_uncore_read(guc_to_gt(guc)->uncore, SOFT_SCRATCH(15)); in guc_get_mmio_msg()
408 intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET)); in uc_init_wopcm()
411 intel_uncore_read(uncore, GUC_WOPCM_SIZE)); in uc_init_wopcm()
421 return (intel_uncore_read(uncore, GUC_WOPCM_SIZE) & GUC_WOPCM_SIZE_LOCKED) || in uc_is_wopcm_locked()
422 (intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET) & GUC_WOPCM_OFFSET_VALID); in uc_is_wopcm_locked()
A Dintel_guc.c99 guc_WARN_ON_ONCE(guc, intel_uncore_read(gt->uncore, GEN8_GT_IIR(2)) & in gen9_enable_guc_interrupts()
409 stamp = intel_uncore_read(gt->uncore, GUCPMTIMESTAMP); in intel_guc_dump_time_info()
552 #define done ({ header = intel_uncore_read(uncore, guc_send_reg(guc, 0)); \ in intel_guc_send_mmio()
599 response_buf[i] = intel_uncore_read(uncore, in intel_guc_send_mmio()
931 u32 status = intel_uncore_read(uncore, GUC_STATUS); in intel_guc_load_status()
944 i, intel_uncore_read(uncore, SOFT_SCRATCH(i))); in intel_guc_load_status()
A Dintel_huc.c336 huc->loaded_via_gsc = intel_uncore_read(gt->uncore, GUC_SHIM_CONTROL2) & in check_huc_loading_mode()
494 intel_uncore_read(uncore, intel_gt_perf_limit_reasons_reg(gt))); in intel_huc_wait_for_auth_complete()
583 status = intel_uncore_read(gt->uncore, huc->status[type].reg); in intel_huc_is_authenticated()
691 intel_uncore_read(gt->uncore, huc->status[INTEL_HUC_AUTH_BY_GUC].reg)); in intel_huc_load_status()
/drivers/gpu/drm/i915/gem/
A Di915_gem_stolen.c105 ggtt_start = intel_uncore_read(uncore, PGTBL_CTL); in adjust_stolen()
207 u32 reg_val = intel_uncore_read(uncore, in g4x_get_stolen_reserved()
242 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); in gen6_get_stolen_reserved()
275 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); in vlv_get_stolen_reserved()
304 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); in gen7_get_stolen_reserved()
331 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); in chv_get_stolen_reserved()
364 u32 reg_val = intel_uncore_read(uncore, GEN6_STOLEN_RESERVED); in bdw_get_stolen_reserved()

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