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Searched refs:interrupt_mask (Results 1 – 18 of 18) sorted by relevance

/drivers/net/wireless/ath/ath5k/
A Ddma.c541 *interrupt_mask = isr; in ath5k_hw_get_isr()
554 *interrupt_mask |= AR5K_INT_FATAL; in ath5k_hw_get_isr()
577 *interrupt_mask = pisr; in ath5k_hw_get_isr()
678 *interrupt_mask |= AR5K_INT_TIM; in ath5k_hw_get_isr()
683 *interrupt_mask |= AR5K_INT_TIM; in ath5k_hw_get_isr()
685 *interrupt_mask |= AR5K_INT_DTIM; in ath5k_hw_get_isr()
699 *interrupt_mask |= AR5K_INT_FATAL; in ath5k_hw_get_isr()
703 *interrupt_mask |= AR5K_INT_BNR; in ath5k_hw_get_isr()
707 *interrupt_mask |= AR5K_INT_QCBRORN; in ath5k_hw_get_isr()
711 *interrupt_mask |= AR5K_INT_QCBRURN; in ath5k_hw_get_isr()
[all …]
A Dath5k.h1516 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
/drivers/ps3/
A Dps3-vuart.c67 u64 interrupt_mask; member
256 priv->interrupt_mask = mask; in ps3_vuart_set_interrupt_mask()
259 PARAM_INTERRUPT_MASK, priv->interrupt_mask); in ps3_vuart_set_interrupt_mask()
282 *status = tmp & priv->interrupt_mask; in ps3_vuart_get_interrupt_status()
285 __func__, __LINE__, priv->interrupt_mask, tmp, *status); in ps3_vuart_get_interrupt_status()
294 return (priv->interrupt_mask & INTERRUPT_MASK_TX) ? 0 in ps3_vuart_enable_interrupt_tx()
295 : ps3_vuart_set_interrupt_mask(dev, priv->interrupt_mask in ps3_vuart_enable_interrupt_tx()
303 return (priv->interrupt_mask & INTERRUPT_MASK_RX) ? 0 in ps3_vuart_enable_interrupt_rx()
304 : ps3_vuart_set_interrupt_mask(dev, priv->interrupt_mask in ps3_vuart_enable_interrupt_rx()
321 return (priv->interrupt_mask & INTERRUPT_MASK_TX) in ps3_vuart_disable_interrupt_tx()
[all …]
/drivers/gpu/drm/i915/gt/
A Dintel_gt_pm_irq.c33 u32 interrupt_mask, in gen6_gt_pm_update_irq() argument
38 WARN_ON(enabled_irq_mask & ~interrupt_mask); in gen6_gt_pm_update_irq()
43 new_val &= ~interrupt_mask; in gen6_gt_pm_update_irq()
44 new_val |= ~enabled_irq_mask & interrupt_mask; in gen6_gt_pm_update_irq()
A Dintel_gt_irq.c490 u32 interrupt_mask, in gen5_gt_update_irq() argument
495 GEM_BUG_ON(enabled_irq_mask & ~interrupt_mask); in gen5_gt_update_irq()
497 gt->gt_imr &= ~interrupt_mask; in gen5_gt_update_irq()
498 gt->gt_imr |= (~enabled_irq_mask & interrupt_mask); in gen5_gt_update_irq()
/drivers/gpu/drm/i915/display/
A Dintel_display_irq.h23 u32 interrupt_mask, u32 enabled_irq_mask);
27 void bdw_update_port_irq(struct intel_display *display, u32 interrupt_mask, u32 enabled_irq_mask);
32 u32 interrupt_mask, u32 enabled_irq_mask);
A Dintel_display_irq.c135 u32 interrupt_mask, u32 enabled_irq_mask) in ilk_update_display_irq() argument
144 new_val &= ~interrupt_mask; in ilk_update_display_irq()
145 new_val |= (~enabled_irq_mask & interrupt_mask); in ilk_update_display_irq()
172 u32 interrupt_mask, u32 enabled_irq_mask) in bdw_update_port_irq() argument
188 new_val &= ~interrupt_mask; in bdw_update_port_irq()
189 new_val |= (~enabled_irq_mask & interrupt_mask); in bdw_update_port_irq()
205 enum pipe pipe, u32 interrupt_mask, in bdw_update_pipe_irq() argument
219 new_val &= ~interrupt_mask; in bdw_update_pipe_irq()
248 u32 interrupt_mask, in ibx_display_interrupt_update() argument
254 sdeimr &= ~interrupt_mask; in ibx_display_interrupt_update()
[all …]
/drivers/uio/
A Duio_hv_generic.c70 channel->inbound.ring_buffer->interrupt_mask = !irq_state; in set_event()
114 chan->inbound.ring_buffer->interrupt_mask = 1; in hv_uio_channel_cb()
187 new_sc->inbound.ring_buffer->interrupt_mask = 1; in hv_uio_new_channel()
231 dev->channel->inbound.ring_buffer->interrupt_mask = 1; in hv_uio_open()
/drivers/media/platform/samsung/exynos4-is/
A Dmipi-csis.c171 u32 interrupt_mask; member
211 u32 interrupt_mask; member
294 val |= state->interrupt_mask; in s5pcsis_enable_interrupts()
296 val &= ~state->interrupt_mask; in s5pcsis_enable_interrupts()
786 state->interrupt_mask = drv_data->interrupt_mask; in s5pcsis_probe()
1005 .interrupt_mask = S5PCSIS_INTMSK_EXYNOS4_EN_ALL,
1009 .interrupt_mask = S5PCSIS_INTMSK_EXYNOS5_EN_ALL,
/drivers/irqchip/
A Dirq-vic.c492 u32 interrupt_mask = ~0; in vic_of_init() local
500 of_property_read_u32(node, "valid-mask", &interrupt_mask); in vic_of_init()
509 __vic_init(regs, parent_irq, 0, interrupt_mask, wakeup_mask, node); in vic_of_init()
/drivers/scsi/isci/
A Dhost.c210 writel(0xFF000000, &ihost->smu_registers->interrupt_mask); in sci_controller_isr()
211 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_isr()
249 writel(0xff, &ihost->smu_registers->interrupt_mask); in sci_controller_error_isr()
250 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_error_isr()
603 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_error_handler()
705 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_enable_interrupts()
711 writel(0xffffffff, &ihost->smu_registers->interrupt_mask); in sci_controller_disable_interrupts()
712 readl(&ihost->smu_registers->interrupt_mask); /* flush */ in sci_controller_disable_interrupts()
1074 writel(0xFF000000, &ihost->smu_registers->interrupt_mask); in sci_controller_completion_handler()
1075 writel(0, &ihost->smu_registers->interrupt_mask); in sci_controller_completion_handler()
A Dregisters.h969 u32 interrupt_mask; member
/drivers/hv/
A Dring_buffer.c58 if (READ_ONCE(rbi->ring_buffer->interrupt_mask)) in hv_signal_on_write()
171 = ring_info->ring_buffer->interrupt_mask; in hv_ringbuffer_get_debuginfo()
A Dvmbus_drv.c1583 ret = sprintf(buf, "%u\n", rbi->ring_buffer->interrupt_mask); in out_mask_show()
1600 ret = sprintf(buf, "%u\n", rbi->ring_buffer->interrupt_mask); in in_mask_show()
/drivers/pinctrl/
A Dpinctrl-amd.c209 char *interrupt_mask; in amd_gpio_dbg_show() local
275 interrupt_mask = "��"; in amd_gpio_dbg_show()
277 interrupt_mask = "��"; in amd_gpio_dbg_show()
286 interrupt_mask, in amd_gpio_dbg_show()
/drivers/soundwire/
A Dcadence_master.c27 static int interrupt_mask; variable
28 module_param_named(cnds_mcp_int_mask, interrupt_mask, int, 0444);
1234 if (interrupt_mask) /* parameter override */ in sdw_cdns_enable_interrupt()
1235 mask = interrupt_mask; in sdw_cdns_enable_interrupt()
/drivers/gpu/drm/amd/amdgpu/
A Ddce_v6_0.c2954 u32 reg_block, interrupt_mask; in dce_v6_0_set_crtc_vblank_interrupt_state() local
2987 interrupt_mask = RREG32(mmINT_MASK + reg_block); in dce_v6_0_set_crtc_vblank_interrupt_state()
2988 interrupt_mask &= ~INT_MASK__VBLANK_INT_MASK; in dce_v6_0_set_crtc_vblank_interrupt_state()
2989 WREG32(mmINT_MASK + reg_block, interrupt_mask); in dce_v6_0_set_crtc_vblank_interrupt_state()
2992 interrupt_mask = RREG32(mmINT_MASK + reg_block); in dce_v6_0_set_crtc_vblank_interrupt_state()
2993 interrupt_mask |= INT_MASK__VBLANK_INT_MASK; in dce_v6_0_set_crtc_vblank_interrupt_state()
2994 WREG32(mmINT_MASK + reg_block, interrupt_mask); in dce_v6_0_set_crtc_vblank_interrupt_state()
/drivers/cpufreq/
A Dintel_pstate.c2048 u64 interrupt_mask = HWP_GUARANTEED_PERF_CHANGE_REQ; in intel_pstate_enable_hwp_interrupt() local
2056 interrupt_mask |= HWP_HIGHEST_PERF_CHANGE_REQ; in intel_pstate_enable_hwp_interrupt()
2059 wrmsrq_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, interrupt_mask); in intel_pstate_enable_hwp_interrupt()

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