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Searched refs:io_base (Results 1 – 25 of 157) sorted by relevance

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/drivers/gpu/drm/meson/
A Dmeson_venc.c1107 priv->io_base + _REG(ENCI_VIDEO_SCH)); in meson_venc_hdmi_mode_set()
1114 priv->io_base + _REG(ENCI_YC_DELAY)); in meson_venc_hdmi_mode_set()
1168 priv->io_base + _REG(ENCI_DE_H_END)); in meson_venc_hdmi_mode_set()
1240 writel_relaxed(hs_begin, priv->io_base in meson_venc_hdmi_mode_set()
1249 writel_relaxed(hs_begin, priv->io_base in meson_venc_hdmi_mode_set()
1333 priv->io_base in meson_venc_hdmi_mode_set()
1415 priv->io_base + _REG(ENCP_DE_H_END)); in meson_venc_hdmi_mode_set()
1434 readl_relaxed(priv->io_base + in meson_venc_hdmi_mode_set()
1920 priv->io_base + _REG(ENCI_VIDEO_SAT)); in meson_venci_cvbs_mode_set()
1926 priv->io_base + _REG(ENCI_VIDEO_HUE)); in meson_venci_cvbs_mode_set()
[all …]
A Dmeson_viu.c130 priv->io_base + in meson_viu_set_osd_matrix()
133 priv->io_base + in meson_viu_set_osd_matrix()
136 priv->io_base + in meson_viu_set_osd_matrix()
204 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
207 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
211 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
215 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
218 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
231 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
234 priv->io_base + _REG(data_port)); in meson_viu_set_osd_lut()
[all …]
A Dmeson_crtc.c272 priv->io_base + in meson_g12a_crtc_enable_osd1()
275 priv->io_base + in meson_g12a_crtc_enable_osd1()
278 priv->io_base + in meson_g12a_crtc_enable_osd1()
281 priv->io_base + in meson_g12a_crtc_enable_osd1()
396 priv->io_base + in meson_crtc_irq()
399 priv->io_base + in meson_crtc_irq()
402 priv->io_base + in meson_crtc_irq()
405 priv->io_base + in meson_crtc_irq()
408 priv->io_base + in meson_crtc_irq()
411 priv->io_base + in meson_crtc_irq()
[all …]
A Dmeson_vpp.c63 priv->io_base + _REG(VPP_OSD_SCALE_COEF)); in meson_vpp_write_scaling_filter_coefs()
85 priv->io_base + _REG(VPP_SCALE_COEF_IDX)); in meson_vpp_write_vd_scaling_filter_coefs()
88 priv->io_base + _REG(VPP_SCALE_COEF)); in meson_vpp_write_vd_scaling_filter_coefs()
98 priv->io_base + _REG(VIU_MISC_CTRL1)); in meson_vpp_init()
102 priv->io_base + _REG(VPP_DUMMY_DATA1)); in meson_vpp_init()
104 priv->io_base + _REG(VPP_DUMMY_DATA)); in meson_vpp_init()
114 priv->io_base + _REG(VPP_OFIFO_SIZE)); in meson_vpp_init()
121 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
125 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
131 priv->io_base + _REG(VPP_MISC)); in meson_vpp_init()
[all …]
A Dmeson_rdma.c39 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
43 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_init()
68 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_setup()
75 priv->io_base + _REG(RDMA_CTRL)); in meson_rdma_stop()
81 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_stop()
113 writel_relaxed(val, priv->io_base + _REG(reg)); in meson_rdma_writel_sync()
122 priv->io_base + _REG(RDMA_AHB_START_ADDR_1)); in meson_rdma_flush()
126 priv->io_base + _REG(RDMA_AHB_END_ADDR_1)); in meson_rdma_flush()
132 priv->io_base + _REG(RDMA_ACCESS_AUTO)); in meson_rdma_flush()
A Dmeson_osd_afbcd.c85 priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
86 writel_relaxed(0, priv->io_base + _REG(VIU_SW_RESET)); in meson_gxm_afbcd_reset()
105 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_enable()
113 priv->io_base + _REG(OSD1_AFBCD_ENABLE)); in meson_gxm_afbcd_disable()
139 priv->io_base + _REG(OSD1_AFBCD_SIZE_IN)); in meson_gxm_afbcd_setup()
142 priv->io_base + _REG(OSD1_AFBCD_HDR_PTR)); in meson_gxm_afbcd_setup()
144 priv->io_base + _REG(OSD1_AFBCD_FRAME_PTR)); in meson_gxm_afbcd_setup()
147 priv->io_base + _REG(OSD1_AFBCD_CHROMA_PTR)); in meson_gxm_afbcd_setup()
163 priv->io_base + _REG(OSD1_AFBCD_CONV_CTRL)); in meson_gxm_afbcd_setup()
302 priv->io_base + _REG(MALI_AFBCD_TOP_CTRL)); in meson_g12a_afbcd_init()
[all …]
/drivers/spi/
A Dspi-sg2044-nor.c94 void __iomem *io_base; member
152 writel(0, spifmc->io_base + SPIFMC_FIFO_PT); in sg2044_spifmc_read_64k()
162 writel(0, spifmc->io_base + SPIFMC_INT_STS); in sg2044_spifmc_read_64k()
188 writel(0, spifmc->io_base + SPIFMC_FIFO_PT); in sg2044_spifmc_read_64k()
234 writel(0, spifmc->io_base + SPIFMC_FIFO_PT); in sg2044_spifmc_write()
243 writel(0, spifmc->io_base + SPIFMC_INT_STS); in sg2044_spifmc_write()
416 writel(0, spifmc->io_base + SPIFMC_DMMR); in sg2044_spifmc_init()
418 reg = readl(spifmc->io_base + SPIFMC_CTRL); in sg2044_spifmc_init()
422 writel(reg, spifmc->io_base + SPIFMC_CTRL); in sg2044_spifmc_init()
454 if (IS_ERR(spifmc->io_base)) in sg2044_spifmc_probe()
[all …]
A Dspi-stm32-qspi.c104 void __iomem *io_base; member
134 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_irq()
135 sr = readl_relaxed(qspi->io_base + QSPI_SR); in stm32_qspi_irq()
140 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
149 writel_relaxed(cr, qspi->io_base + QSPI_CR); in stm32_qspi_irq()
192 tx_fifo(buf++, qspi->io_base + QSPI_DR); in stm32_qspi_tx_poll()
247 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_tx_dma()
312 cr = readl_relaxed(qspi->io_base + QSPI_CR); in stm32_qspi_wait_cmd()
373 qspi->io_base + QSPI_DLR); in stm32_qspi_send()
775 if (IS_ERR(qspi->io_base)) in stm32_qspi_probe()
[all …]
/drivers/crypto/hisilicon/zip/
A Ddae_main.c71 val = readl(qm->io_base + DAE_MEM_START_OFFSET); in hisi_dae_set_user_domain()
73 writel(val, qm->io_base + DAE_MEM_START_OFFSET); in hisi_dae_set_user_domain()
112 axi_val = readl(qm->io_base + DAE_AXI_CFG_OFFSET); in hisi_dae_master_ooo_ctrl()
121 writel(axi_val, qm->io_base + DAE_AXI_CFG_OFFSET); in hisi_dae_master_ooo_ctrl()
122 writel(err_val, qm->io_base + DAE_ERR_SHUTDOWN_OFFSET); in hisi_dae_master_ooo_ctrl()
149 writel(0, qm->io_base + DAE_ERR_ENABLE_OFFSET); in hisi_dae_hw_error_disable()
155 return readl(qm->io_base + DAE_ERR_STATUS_OFFSET); in hisi_dae_get_hw_err_status()
163 writel(err_sts, qm->io_base + DAE_ERR_SOURCE_OFFSET); in hisi_dae_clear_hw_err_status()
238 val = readl(qm->io_base + DAE_AM_CTRL_GLOBAL_OFFSET); in hisi_dae_close_axi_master_ooo()
240 writel(val, qm->io_base + DAE_AM_CTRL_GLOBAL_OFFSET); in hisi_dae_close_axi_master_ooo()
[all …]
A Dzip_main.c484 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_open_sva_prefetch()
503 writel(val, qm->io_base + HZIP_PREFETCH_CFG); in hisi_zip_close_sva_prefetch()
530 void __iomem *base = qm->io_base; in hisi_zip_set_user_domain_and_cache()
614 qm->io_base + HZIP_CORE_INT_MASK_REG); in hisi_zip_hw_error_enable()
807 return qm->io_base + HZIP_CORE_DFX_BASE + in get_zip_core_addr()
993 void __iomem *io_base; in hisi_zip_show_last_regs_init() local
1008 io_base = qm->io_base + hzip_com_dfx_regs[i].offset; in hisi_zip_show_last_regs_init()
1013 io_base = get_zip_core_addr(qm, i); in hisi_zip_show_last_regs_init()
1017 io_base + hzip_dump_dfx_regs[j].offset); in hisi_zip_show_last_regs_init()
1096 err_val = readl(qm->io_base + in hisi_zip_log_hw_error()
[all …]
/drivers/watchdog/
A Dni903x_wdt.c40 u16 io_base; member
58 u8 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_start()
85 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
87 outb(control, wdt->io_base + NIWD_CONTROL); in ni903x_wdd_get_timeleft()
89 counter2 = inb(wdt->io_base + NIWD_COUNTER2); in ni903x_wdd_get_timeleft()
103 control = inb(wdt->io_base + NIWD_CONTROL); in ni903x_wdd_ping()
114 wdt->io_base + NIWD_CONTROL); in ni903x_wdd_start()
138 if (wdt->io_base != 0) { in ni903x_resources()
143 wdt->io_base = res->data.io.minimum; in ni903x_resources()
219 wdt->io_base + NIWD_CONTROL); in ni903x_acpi_add()
[all …]
A Dnic7018_wdt.c47 u16 io_base; member
97 wdt->io_base + WDT_PRESET_PRESCALE); in nic7018_set_timeout()
115 outb(1, wdt->io_base + WDT_RELOAD_PORT); in nic7018_start()
117 control = inb(wdt->io_base + WDT_CTRL); in nic7018_start()
127 outb(0, wdt->io_base + WDT_CTRL); in nic7018_stop()
128 outb(0, wdt->io_base + WDT_RELOAD_CTRL); in nic7018_stop()
138 outb(1, wdt->io_base + WDT_RELOAD_PORT); in nic7018_ping()
195 wdt->io_base = io_rc->start; in nic7018_probe()
213 outb(LOCK, wdt->io_base + WDT_REG_LOCK); in nic7018_probe()
218 wdt->io_base, timeout, nowayout); in nic7018_probe()
[all …]
/drivers/crypto/hisilicon/sec2/
A Dsec_main.c472 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
475 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
478 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
482 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
485 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
488 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
490 reg = readl_relaxed(qm->io_base + in sec_engine_sva_config()
497 writel_relaxed(reg, qm->io_base + in sec_engine_sva_config()
699 writel(ce, qm->io_base + SEC_RAS_CE_REG); in sec_hw_error_enable()
902 regset->base = qm->io_base; in sec_core_debug_init()
[all …]
/drivers/crypto/intel/keembay/
A Docs-hcu.c182 writel(0xFFFFFFFF, hcu_dev->io_base + OCS_HCU_ISR); in ocs_hcu_done_irq_en()
186 hcu_dev->io_base + OCS_HCU_IER); in ocs_hcu_done_irq_en()
196 hcu_dev->io_base + OCS_HCU_DMA_MSI_IER); in ocs_hcu_dma_irq_en()
270 chain[i] = readl(hcu_dev->io_base + OCS_HCU_CHAIN); in ocs_hcu_get_intermediate_data()
301 writel(chain[i], hcu_dev->io_base + OCS_HCU_CHAIN); in ocs_hcu_set_intermediate_data()
328 chain[i] = readl(hcu_dev->io_base + OCS_HCU_CHAIN); in ocs_hcu_get_digest()
365 writel(cfg, hcu_dev->io_base + OCS_HCU_MODE); in ocs_hcu_hw_cfg()
472 writel(0, hcu_dev->io_base + OCS_HCU_DMA_SRC_SIZE); in ocs_hcu_ll_dma_start()
473 writel(0, hcu_dev->io_base + OCS_HCU_DMA_DST_SIZE); in ocs_hcu_ll_dma_start()
815 hcu_irq = readl(hcu_dev->io_base + OCS_HCU_ISR); in ocs_hcu_irq_handler()
[all …]
/drivers/crypto/hisilicon/hpre/
A Dhpre_main.c617 val = readl(qm->io_base + HPRE_CLKGATE_CTL); in hpre_enable_clock_gate()
688 qm->io_base + HPRE_TYPES_ENB); in hpre_set_user_domain_and_cache()
693 writel(0x0, qm->io_base + HPRE_BD_ENDIAN); in hpre_set_user_domain_and_cache()
695 writel(0x0, qm->io_base + HPRE_ECC_BYPASS); in hpre_set_user_domain_and_cache()
796 writel(ce, qm->io_base + HPRE_RAS_CE_ENB); in hpre_hw_error_enable()
1017 regset->base = qm->io_base; in hpre_pf_comm_regs_debugfs_init()
1256 void __iomem *io_base; in hpre_show_last_regs_init() local
1274 io_base = qm->io_base + hpre_cluster_offsets[i]; in hpre_show_last_regs_init()
1302 void __iomem *io_base; in hpre_show_last_dfx_regs() local
1323 io_base = qm->io_base + hpre_cluster_offsets[i]; in hpre_show_last_dfx_regs()
[all …]
/drivers/fpga/
A Dts73xx-fpga.c31 void __iomem *io_base; member
42 writeb(0, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_init()
65 writeb(buf[i], priv->io_base + TS73XX_FPGA_DATA_REG); in ts73xx_fpga_write()
79 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
81 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
84 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
86 writeb(reg, priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
88 reg = readb(priv->io_base + TS73XX_FPGA_CONFIG_REG); in ts73xx_fpga_write_complete()
113 priv->io_base = devm_platform_ioremap_resource(pdev, 0); in ts73xx_fpga_probe()
114 if (IS_ERR(priv->io_base)) in ts73xx_fpga_probe()
[all …]
/drivers/mtd/spi-nor/controllers/
A Dnxp-spifi.c56 void __iomem *io_base; member
140 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_read_reg()
164 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_write_reg()
199 writel(to, spifi->io_base + SPIFI_ADDR); in nxp_spifi_write()
206 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_write()
228 writel(offs, spifi->io_base + SPIFI_ADDR); in nxp_spifi_erase()
233 writel(cmd, spifi->io_base + SPIFI_CMD); in nxp_spifi_erase()
390 if (IS_ERR(spifi->io_base)) in nxp_spifi_probe()
391 return PTR_ERR(spifi->io_base); in nxp_spifi_probe()
414 writel(0, spifi->io_base + SPIFI_IDATA); in nxp_spifi_probe()
[all …]
/drivers/hwspinlock/
A Du8500_hsem.c90 void __iomem *io_base; in u8500_hsem_probe() local
97 io_base = devm_platform_ioremap_resource(pdev, 0); in u8500_hsem_probe()
98 if (IS_ERR(io_base)) in u8500_hsem_probe()
99 return PTR_ERR(io_base); in u8500_hsem_probe()
102 val = readl(io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
103 writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG); in u8500_hsem_probe()
106 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_probe()
116 hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i; in u8500_hsem_probe()
126 void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET; in u8500_hsem_remove() local
129 writel(0xFFFF, io_base + HSEM_ICRALL); in u8500_hsem_remove()
/drivers/mtd/nand/raw/
A Dlpc32xx_slc.c219 void __iomem *io_base; member
245 writel(0, SLC_CFG(host->io_base)); in lpc32xx_nand_setup()
246 writel(0, SLC_IEN(host->io_base)); in lpc32xx_nand_setup()
248 SLC_ICR(host->io_base)); in lpc32xx_nand_setup()
264 writel(tmp, SLC_TAC(host->io_base)); in lpc32xx_nand_setup()
516 SLC_CFG(host->io_base)); in lpc32xx_xfer()
527 SLC_CTRL(host->io_base)); in lpc32xx_xfer()
571 readl(SLC_ECC(host->io_base)); in lpc32xx_xfer()
585 SLC_CTRL(host->io_base)); in lpc32xx_xfer()
844 if (IS_ERR(host->io_base)) in lpc32xx_nand_probe()
[all …]
A Dlpc32xx_mlc.c180 void __iomem *io_base; member
250 writel(tmp, MLC_ICR(host->io_base)); in lpc32xx_nand_setup()
269 MLC_IRQ_MR(host->io_base)); in lpc32xx_nand_setup()
285 writel(cmd, MLC_CMD(host->io_base)); in lpc32xx_nand_cmd_ctrl()
298 if ((readb(MLC_ISR(host->io_base)) & in lpc32xx_nand_device_ready()
483 readl(MLC_BUFF(host->io_base)); in lpc32xx_read_page()
489 readl(MLC_BUFF(host->io_base)); in lpc32xx_read_page()
531 MLC_BUFF(host->io_base)); in lpc32xx_write_page_lowlevel()
704 if (IS_ERR(host->io_base)) in lpc32xx_nand_probe()
705 return PTR_ERR(host->io_base); in lpc32xx_nand_probe()
[all …]
/drivers/mtd/devices/
A Dspear_smi.c174 void __iomem *io_base; member
235 dev->io_base + SMI_CR2); in spear_smi_read_sr()
249 writel(0, dev->io_base + SMI_CR2); in spear_smi_read_sr()
307 writel(0, dev->io_base + SMI_SR); in spear_smi_int_handler()
343 writel(0, dev->io_base + SMI_SR); in spear_smi_hw_init()
345 writel(val, dev->io_base + SMI_CR1); in spear_smi_hw_init()
399 writel(0, dev->io_base + SMI_CR2); in spear_smi_write_enable()
467 dev->io_base + SMI_CR2); in spear_smi_erase_sector()
480 writel(0, dev->io_base + SMI_CR2); in spear_smi_erase_sector()
978 if (IS_ERR(dev->io_base)) { in spear_smi_probe()
[all …]
/drivers/gpu/drm/xe/
A Dxe_ttm_stolen_mgr.c33 resource_size_t io_base; member
179 if (gscpsmi_base >= mgr->io_base && in detect_bar2_integrated()
180 gscpsmi_base < mgr->io_base + stolen_size) { in detect_bar2_integrated()
183 mgr->io_base + stolen_size - gscpsmi_base); in detect_bar2_integrated()
184 stolen_size = gscpsmi_base - mgr->io_base; in detect_bar2_integrated()
267 XE_WARN_ON(!mgr->io_base); in xe_ttm_stolen_io_offset()
270 return mgr->io_base + xe_bo_ggtt_addr(bo) + offset; in xe_ttm_stolen_io_offset()
273 return mgr->io_base + cur.start; in xe_ttm_stolen_io_offset()
282 if (!mgr->io_base) in __xe_ttm_stolen_io_mem_reserve_bar2()
293 mem->bus.offset += mgr->io_base; in __xe_ttm_stolen_io_mem_reserve_bar2()
[all …]
/drivers/input/keyboard/
A Dspear-keyboard.c56 void __iomem *io_base; member
75 sts = readl_relaxed(kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
85 val = readl_relaxed(kbd->io_base + DATA_REG) & in spear_kbd_interrupt()
96 writel_relaxed(0, kbd->io_base + STATUS_REG); in spear_kbd_interrupt()
120 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
121 writel_relaxed(1, kbd->io_base + STATUS_REG); in spear_kbd_open()
124 val = readl_relaxed(kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
126 writel_relaxed(val, kbd->io_base + MODE_CTL_REG); in spear_kbd_open()
221 if (IS_ERR(kbd->io_base)) in spear_kbd_probe()
222 return PTR_ERR(kbd->io_base); in spear_kbd_probe()
[all …]
/drivers/mfd/
A Dtqmx86.c204 void __iomem *io_base, u8 reg_shift) in tqmx86_setup_irq() argument
227 val = ioread8(io_base + TQMX86_REG_IO_EXT_INT); in tqmx86_setup_irq()
231 iowrite8(val, io_base + TQMX86_REG_IO_EXT_INT); in tqmx86_setup_irq()
232 readback = ioread8(io_base + TQMX86_REG_IO_EXT_INT); in tqmx86_setup_irq()
246 void __iomem *io_base; in tqmx86_probe() local
250 if (!io_base) in tqmx86_probe()
253 board_id = ioread8(io_base + TQMX86_REG_BOARD_ID); in tqmx86_probe()
254 sauc = ioread8(io_base + TQMX86_REG_SAUC); in tqmx86_probe()
256 rev = ioread8(io_base + TQMX86_REG_BOARD_REV); in tqmx86_probe()
270 err = tqmx86_setup_irq(dev, "GPIO", gpio_irq, io_base, in tqmx86_probe()
[all …]
/drivers/net/ethernet/hisilicon/hns3/hns3pf/
A Dhclge_ptp.c46 hdev->ptp->io_base + HCLGE_PTP_CYCLE_QUO_REG); in hclge_ptp_adjfine()
50 hdev->ptp->io_base + HCLGE_PTP_CYCLE_CFG_REG); in hclge_ptp_adjfine()
85 ns = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_NSEC_REG) & in hclge_ptp_clean_tx_hwts()
87 lo = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_SEC_L_REG); in hclge_ptp_clean_tx_hwts()
88 hi = readl(hdev->ptp->io_base + HCLGE_PTP_TX_TS_SEC_H_REG) & in hclge_ptp_clean_tx_hwts()
90 hdev->ptp->last_tx_seqid = readl(hdev->ptp->io_base + in hclge_ptp_clean_tx_hwts()
161 hdev->ptp->io_base + HCLGE_PTP_TIME_SEC_H_REG); in hclge_ptp_settime()
163 hdev->ptp->io_base + HCLGE_PTP_TIME_SEC_L_REG); in hclge_ptp_settime()
166 hdev->ptp->io_base + HCLGE_PTP_TIME_SYNC_REG); in hclge_ptp_settime()
201 hdev->ptp->io_base + HCLGE_PTP_TIME_ADJ_REG); in hclge_ptp_adjtime()
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