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Searched refs:ioaddr (Results 1 – 25 of 284) sorted by relevance

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/drivers/net/ethernet/realtek/
A Datp.c232 long ioaddr = *port; in atp_init() local
236 if (atp_probe1(ioaddr) == 0) in atp_init()
316 else if (ioaddr == 0x378) in atp_probe1()
323 dev->base_addr = ioaddr; in atp_probe1()
370 long ioaddr = dev->base_addr; in get_node_ID() local
458 long ioaddr = dev->base_addr; in hardware_init() local
569 write_reg(ioaddr, IMR, 0); in atp_send_packet()
598 long ioaddr; in atp_interrupt() local
603 ioaddr = dev->base_addr; in atp_interrupt()
613 write_reg(ioaddr, IMR, 0); in atp_interrupt()
[all …]
A Datp.h112 outb(Ctrl_LNibRead, ioaddr + PAR_CONTROL); in read_byte_mode0()
113 inbyte(ioaddr + PAR_STATUS); in read_byte_mode0()
127 inbyte(ioaddr + PAR_STATUS); in read_byte_mode2()
139 outb(RdAddr | MAR, ioaddr + PAR_DATA); in read_byte_mode4()
150 outb(RdAddr | MAR, ioaddr + PAR_DATA); in read_byte_mode6()
151 inbyte(ioaddr + PAR_STATUS); in read_byte_mode6()
154 inbyte(ioaddr + PAR_STATUS); in read_byte_mode6()
226 outb(value & 0x0f, ioaddr + PAR_DATA); in write_byte_mode0()
232 outb(value & 0x0f, ioaddr + PAR_DATA); in write_byte_mode1()
241 outb(value & 0x0f, ioaddr + PAR_DATA); in write_word_mode0()
[all …]
/drivers/net/ethernet/smsc/
A Dsmc9194.c338 outw( inw( ioaddr + CONTROL ) | CTL_AUTO_RELEASE , ioaddr + CONTROL ); in smc_reset()
398 outw( inw( ioaddr + CONTROL ), CTL_POWERDOWN, ioaddr + CONTROL ); in smc_shutdown()
967 smc_reset( ioaddr ); in smc_probe()
1059 smc_reset( ioaddr ); in smc_open()
1067 ioaddr + CONFIG ); in smc_open()
1071 ioaddr + CONFIG ); in smc_open()
1286 outw( inw( ioaddr + TCR ) | TCR_ENABLE, ioaddr + TCR ); in smc_tx()
1458 outw( inw(ioaddr + RCR ) | RCR_PROMISC, ioaddr + RCR ); in smc_set_multicast_list()
1470 outw( inw(ioaddr + RCR ) | RCR_ALMUL, ioaddr + RCR ); in smc_set_multicast_list()
1480 ioaddr + RCR ); in smc_set_multicast_list()
[all …]
/drivers/net/ethernet/samsung/sxgbe/
A Dsxgbe_core.c21 static void sxgbe_core_init(void __iomem *ioaddr) in sxgbe_core_init() argument
26 regval = readl(ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
31 writel(regval, ioaddr + SXGBE_CORE_TX_CONFIG_REG); in sxgbe_core_init()
34 regval = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
40 writel(regval, ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_core_init()
144 return readl(ioaddr + SXGBE_CORE_VERSION_REG); in sxgbe_get_controller_version()
170 reg_val = readl(ioaddr + SXGBE_CORE_RX_CTL0_REG); in sxgbe_core_enable_rxqueue()
243 ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_enable_rx_csum()
245 writel(ctrl, ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_enable_rx_csum()
252 ctrl = readl(ioaddr + SXGBE_CORE_RX_CONFIG_REG); in sxgbe_disable_rx_csum()
[all …]
A Dsxgbe_mtl.c25 reg_val = readl(ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
40 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
50 writel(reg_val, ioaddr + SXGBE_MTL_OP_MODE_REG); in sxgbe_mtl_init()
54 static void sxgbe_mtl_dma_dm_rxqueue(void __iomem *ioaddr) in sxgbe_mtl_dma_dm_rxqueue() argument
56 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP0_REG); in sxgbe_mtl_dma_dm_rxqueue()
57 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP1_REG); in sxgbe_mtl_dma_dm_rxqueue()
58 writel(RX_QUEUE_DYNAMIC, ioaddr + SXGBE_MTL_RXQ_DMAMAP2_REG); in sxgbe_mtl_dma_dm_rxqueue()
68 reg_val = readl(ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_txfifosize()
70 writel(reg_val, ioaddr + SXGBE_MTL_TXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_txfifosize()
80 reg_val = readl(ioaddr + SXGBE_MTL_RXQ_OPMODE_REG(queue_num)); in sxgbe_mtl_set_rxfifosize()
[all …]
A Dsxgbe_dma.c25 reg_val = readl(ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
38 writel(reg_val, ioaddr + SXGBE_DMA_SYSBUS_MODE_REG); in sxgbe_dma_init()
50 reg_val = readl(ioaddr + SXGBE_DMA_CHA_CTL_REG(cha_num)); in sxgbe_dma_channel_init()
67 ioaddr + SXGBE_DMA_CHA_TXDESC_HADD_REG(cha_num)); in sxgbe_dma_channel_init()
69 ioaddr + SXGBE_DMA_CHA_TXDESC_LADD_REG(cha_num)); in sxgbe_dma_channel_init()
72 ioaddr + SXGBE_DMA_CHA_RXDESC_HADD_REG(cha_num)); in sxgbe_dma_channel_init()
74 ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num)); in sxgbe_dma_channel_init()
86 ioaddr + SXGBE_DMA_CHA_RXDESC_LADD_REG(cha_num)); in sxgbe_dma_channel_init()
93 ioaddr + SXGBE_DMA_CHA_INT_ENABLE_REG(cha_num)); in sxgbe_dma_channel_init()
127 ioaddr + SXGBE_DMA_CHA_TXCTL_REG(cnum)); in sxgbe_dma_start_tx()
[all …]
/drivers/net/ethernet/stmicro/stmmac/
A Ddwxgmac2_dma.c13 u32 value = readl(ioaddr + XGMAC_DMA_MODE); in dwxgmac2_dma_reset()
37 void __iomem *ioaddr, in dwxgmac2_dma_init_chan() argument
50 void __iomem *ioaddr, in dwxgmac2_dma_init_rx_chan() argument
67 void __iomem *ioaddr, in dwxgmac2_dma_init_tx_chan() argument
143 reg_space[i] = readl(ioaddr + i * 4); in dwxgmac2_dma_dump_regs()
256 void __iomem *ioaddr, u32 chan, in dwxgmac2_enable_dma_irq() argument
270 void __iomem *ioaddr, u32 chan, in dwxgmac2_disable_dma_irq() argument
284 void __iomem *ioaddr, u32 chan) in dwxgmac2_dma_start_tx() argument
292 value = readl(ioaddr + XGMAC_TX_CONFIG); in dwxgmac2_dma_start_tx()
312 void __iomem *ioaddr, u32 chan) in dwxgmac2_dma_start_rx() argument
[all …]
A Ddwxgmac2_core.c20 void __iomem *ioaddr = hw->pcsr; in dwxgmac2_core_init() local
71 void __iomem *ioaddr = hw->pcsr; in dwxgmac2_rx_ipc() local
87 void __iomem *ioaddr = hw->pcsr; in dwxgmac2_rx_queue_enable() local
101 void __iomem *ioaddr = hw->pcsr; in dwxgmac2_rx_queue_prio() local
149 value = readl(ioaddr + reg); in dwxgmac2_tx_queue_prio()
153 writel(value, ioaddr + reg); in dwxgmac2_tx_queue_prio()
265 value = readl(ioaddr + reg); in dwxgmac2_map_mtl_to_dma()
269 writel(value, ioaddr + reg); in dwxgmac2_map_mtl_to_dma()
314 readl(ioaddr + XGMAC_PMT); in dwxgmac2_host_irq_status()
1526 mac->pcsr = priv->ioaddr; in dwxgmac2_setup()
[all …]
A Ddwmac4_lib.c16 int dwmac4_dma_reset(void __iomem *ioaddr) in dwmac4_dma_reset() argument
18 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
22 writel(value, ioaddr + DMA_BUS_MODE); in dwmac4_dma_reset()
54 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_dma_start_tx()
56 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_dma_start_tx()
81 value = readl(ioaddr + GMAC_CONFIG); in dwmac4_dma_start_rx()
83 writel(value, ioaddr + GMAC_CONFIG); in dwmac4_dma_start_rx()
240 writel(data, ioaddr + low); in stmmac_dwmac4_set_mac_addr()
255 writel(value, ioaddr + GMAC_CONFIG); in stmmac_dwmac4_set_mac()
264 hi_addr = readl(ioaddr + high); in stmmac_dwmac4_get_mac_addr()
[all …]
A Ddwmac5.c78 void __iomem *ioaddr, bool correctable, in dwmac5_handle_mac_err() argument
126 void __iomem *ioaddr, bool correctable, in dwmac5_handle_mtl_err() argument
174 void __iomem *ioaddr, bool correctable, in dwmac5_handle_dma_err() argument
209 value = readl(ioaddr + MTL_ECC_CONTROL); in dwmac5_safety_feat_config()
442 old_val = readl(ioaddr + GMAC_CONFIG); in dwmac5_rxp_config()
444 writel(val, ioaddr + GMAC_CONFIG); in dwmac5_rxp_config()
447 ret = dwmac5_rxp_disable(ioaddr); in dwmac5_rxp_config()
512 dwmac5_rxp_enable(ioaddr); in dwmac5_rxp_config()
516 writel(old_val, ioaddr + GMAC_CONFIG); in dwmac5_rxp_config()
546 writel(val, ioaddr + MAC_PPS_CONTROL); in dwmac5_flex_pps_config()
[all …]
A Ddwmac4_core.c29 void __iomem *ioaddr = hw->pcsr; in dwmac4_core_init() local
81 void __iomem *ioaddr = hw->pcsr; in dwmac4_rx_queue_enable() local
96 void __iomem *ioaddr = hw->pcsr; in dwmac4_rx_queue_priority() local
137 void __iomem *ioaddr = hw->pcsr; in dwmac4_tx_queue_priority() local
157 void __iomem *ioaddr = hw->pcsr; in dwmac4_rx_queue_routing() local
190 void __iomem *ioaddr = hw->pcsr; in dwmac4_prog_mtl_rx_algorithms() local
211 void __iomem *ioaddr = hw->pcsr; in dwmac4_prog_mtl_tx_algorithms() local
359 writel(pmt, ioaddr + GMAC_PMT); in dwmac4_pmt()
672 readl(ioaddr + GMAC_PMT); in dwmac4_irq_status()
697 dwmac4_phystatus(ioaddr, x); in dwmac4_irq_status()
[all …]
A Ddwmac4_dma.c20 u32 value = readl(ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_axi()
69 writel(value, ioaddr + DMA_SYS_BUS_MODE); in dwmac4_dma_axi()
73 void __iomem *ioaddr, in dwmac4_dma_init_rx_chan() argument
94 void __iomem *ioaddr, in dwmac4_dma_init_tx_chan() argument
119 void __iomem *ioaddr, in dwmac4_dma_init_channel() argument
137 void __iomem *ioaddr, in dwmac410_dma_init_channel() argument
176 value = readl(ioaddr + DMA_BUS_MODE); in dwmac4_dma_init()
186 writel(value, ioaddr + DMA_BUS_MODE); in dwmac4_dma_init()
191 void __iomem *ioaddr, u32 channel, in _dwmac4_dump_dma_regs() argument
537 value = readl(ioaddr + GMAC_EXT_CFG1); in dwmac4_enable_sph()
[all …]
A Ddwmac_lib.c17 int dwmac_dma_reset(void __iomem *ioaddr) in dwmac_dma_reset() argument
19 u32 value = readl(ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
23 writel(value, ioaddr + DMA_BUS_MODE); in dwmac_dma_reset()
67 writel(value, ioaddr + DMA_CHAN_CONTROL(chan)); in dwmac_dma_start_tx()
214 u32 value = readl(ioaddr + DMA_INTR_ENA); in dwmac_dma_interrupt()
245 u32 csr6 = readl(ioaddr + DMA_CONTROL); in dwmac_dma_flush_tx_fifo()
263 writel(data, ioaddr + low); in stmmac_set_mac_addr()
272 old_val = readl(ioaddr + MAC_CTRL_REG); in stmmac_set_mac()
281 writel(value, ioaddr + MAC_CTRL_REG); in stmmac_set_mac()
290 hi_addr = readl(ioaddr + high); in stmmac_get_mac_addr()
[all …]
A Dstmmac_hwtstamp.c36 writel(regval, ioaddr + PTP_TCR); in config_hw_tstamping()
90 val = readl(ioaddr + PTP_TCR); in hwtstamp_correct_latency()
122 writel(sec, ioaddr + PTP_STSUR); in init_systime()
125 value = readl(ioaddr + PTP_TCR); in init_systime()
127 writel(value, ioaddr + PTP_TCR); in init_systime()
140 writel(addend, ioaddr + PTP_TAR); in config_addend()
142 value = readl(ioaddr + PTP_TCR); in config_addend()
144 writel(value, ioaddr + PTP_TCR); in config_addend()
180 writel(sec, ioaddr + PTP_STSUR); in adjust_systime()
185 value = readl(ioaddr + PTP_TCR); in adjust_systime()
[all …]
/drivers/net/ethernet/3com/
A D3c509.c672 dev->irq, ioaddr + EL3_STATUS, inw(ioaddr + EL3_STATUS)); in el3_open()
690 dev->name, inb(ioaddr + TX_STATUS), inw(ioaddr + EL3_STATUS), in el3_tx_timeout()
899 inw(ioaddr + 12); in update_stats()
914 inw(ioaddr+EL3_STATUS), inw(ioaddr+RX_STATUS)); in el3_rx()
1214 outw(inw(ioaddr + WN4_MEDIA) & ~MEDIA_TP, ioaddr + WN4_MEDIA); in el3_down()
1280 outw(inw(ioaddr + WN4_MEDIA) | MEDIA_TP, ioaddr + WN4_MEDIA); in el3_up()
1287 inb(ioaddr + i); in el3_up()
1288 inw(ioaddr + 10); in el3_up()
1289 inw(ioaddr + 12); in el3_up()
1320 int ioaddr; in el3_suspend() local
[all …]
A D3c574_cs.c309 unsigned int ioaddr; in tc574_config() local
477 inw(ioaddr+RxStatus), inb(ioaddr+TxStatus), in dump_status()
481 inw(ioaddr+0x04), inw(ioaddr+0x06), in dump_status()
482 inw(ioaddr+0x08), inw(ioaddr+0x0a)); in dump_status()
633 inb(ioaddr + i); in tc574_reset()
634 inw(ioaddr + 10); in tc574_reset()
635 inw(ioaddr + 12); in tc574_reset()
637 inb(ioaddr + 12); in tc574_reset()
638 inb(ioaddr + 13); in tc574_reset()
666 ioaddr + EL3_CMD); in tc574_reset()
[all …]
A D3c515.c439 if ((inw(ioaddr + 0x2002) & 0x1f0) != (ioaddr & 0x1f0)) { in check_device()
474 static int ioaddr; in corkscrew_scan() local
522 inl(ioaddr + 0x2002), inw(ioaddr + 0x2000)); in corkscrew_scan()
536 for (ioaddr = 0x100; ioaddr < 0x400; ioaddr += 0x20) { in corkscrew_scan()
541 inl(ioaddr + 0x2002), inw(ioaddr + 0x2000)); in corkscrew_scan()
791 inb(ioaddr + i); in corkscrew_open()
792 inw(ioaddr + 10); in corkscrew_open()
793 inw(ioaddr + 12); in corkscrew_open()
796 inb(ioaddr + 12); in corkscrew_open()
1261 inw(ioaddr + EL3_STATUS), inw(ioaddr + RxStatus)); in corkscrew_rx()
[all …]
A D3c589_cs.c439 inw(ioaddr+EL3_STATUS), inw(ioaddr+RX_STATUS), in dump_status()
440 inb(ioaddr+TX_STATUS), inw(ioaddr+TX_FREE)); in dump_status()
443 inw(ioaddr+0x04), inw(ioaddr+0x06), inw(ioaddr+0x08), in dump_status()
469 inb(ioaddr+i); in tc589_reset()
470 inw(ioaddr + 10); in tc589_reset()
471 inw(ioaddr + 12); in tc589_reset()
807 inb(ioaddr + 2); in update_stats()
813 inb(ioaddr + 7); in update_stats()
815 inb(ioaddr + 8); in update_stats()
817 inw(ioaddr + 10); in update_stats()
[all …]
/drivers/net/arcnet/
A Dcom90io.c73 int ioaddr = dev->base_addr; in get_buffer_byte() local
85 int ioaddr = dev->base_addr; in put_buffer_byte() local
98 int ioaddr = dev->base_addr; in get_whole_buffer() local
114 int ioaddr = dev->base_addr; in put_whole_buffer() local
140 if (!ioaddr) { in com90io_probe()
146 ioaddr, ioaddr + ARCNET_TOTAL_SIZE - 1); in com90io_probe()
151 ioaddr); in com90io_probe()
224 int ioaddr = dev->base_addr; in com90io_found() local
282 short ioaddr = dev->base_addr; in com90io_reset() local
313 short ioaddr = dev->base_addr; in com90io_command() local
[all …]
A Dcom20020.c94 int ioaddr = dev->base_addr, status; in com20020_check() local
156 int ioaddr = dev->base_addr; in com20020_set_hwaddr() local
169 int ioaddr = dev->base_addr; in com20020_netdev_open() local
180 int ioaddr = dev->base_addr; in com20020_netdev_close() local
206 int ioaddr = dev->base_addr; in com20020_found() local
285 u_int ioaddr = dev->base_addr; in com20020_reset() local
334 u_int ioaddr = dev->base_addr; in com20020_setmask() local
342 u_int ioaddr = dev->base_addr; in com20020_command() local
349 u_int ioaddr = dev->base_addr; in com20020_status() local
358 int ioaddr = dev->base_addr; in com20020_close() local
[all …]
/drivers/rtc/
A Drtc-stk17ta8.c61 void __iomem *ioaddr; member
75 void __iomem *ioaddr = pdata->ioaddr; in stk17ta8_rtc_set_time() local
97 void __iomem *ioaddr = pdata->ioaddr; in stk17ta8_rtc_read_time() local
132 void __iomem *ioaddr = pdata->ioaddr; in stk17ta8_rtc_update_alarm() local
193 void __iomem *ioaddr = pdata->ioaddr; in stk17ta8_rtc_interrupt() local
237 void __iomem *ioaddr = pdata->ioaddr; in stk17ta8_nvram_read() local
249 void __iomem *ioaddr = pdata->ioaddr; in stk17ta8_nvram_write() local
262 void __iomem *ioaddr; in stk17ta8_rtc_probe() local
278 if (IS_ERR(ioaddr)) in stk17ta8_rtc_probe()
279 return PTR_ERR(ioaddr); in stk17ta8_rtc_probe()
[all …]
A Drtc-ds1553.c60 void __iomem *ioaddr; member
74 void __iomem *ioaddr = pdata->ioaddr; in ds1553_rtc_set_time() local
98 void __iomem *ioaddr = pdata->ioaddr; in ds1553_rtc_read_time() local
130 void __iomem *ioaddr = pdata->ioaddr; in ds1553_rtc_update_alarm() local
185 void __iomem *ioaddr = pdata->ioaddr; in ds1553_rtc_interrupt() local
229 void __iomem *ioaddr = pdata->ioaddr; in ds1553_nvram_read() local
242 void __iomem *ioaddr = pdata->ioaddr; in ds1553_nvram_write() local
254 void __iomem *ioaddr; in ds1553_rtc_probe() local
271 if (IS_ERR(ioaddr)) in ds1553_rtc_probe()
272 return PTR_ERR(ioaddr); in ds1553_rtc_probe()
[all …]
A Drtc-ds1742.c93 hour = readb(ioaddr + RTC_HOURS); in ds1742_rtc_read_time()
94 day = readb(ioaddr + RTC_DATE); in ds1742_rtc_read_time()
97 year = readb(ioaddr + RTC_YEAR); in ds1742_rtc_read_time()
99 writeb(0, ioaddr + RTC_CONTROL); in ds1742_rtc_read_time()
125 *buf++ = readb(ioaddr + pos++); in ds1742_nvram_read()
137 writeb(*buf++, ioaddr + pos++); in ds1742_nvram_write()
147 void __iomem *ioaddr; in ds1742_rtc_probe() local
161 if (IS_ERR(ioaddr)) in ds1742_rtc_probe()
162 return PTR_ERR(ioaddr); in ds1742_rtc_probe()
164 pdata->ioaddr_nvram = ioaddr; in ds1742_rtc_probe()
[all …]
/drivers/net/ethernet/fujitsu/
A Dfmvj18x_cs.c303 unsigned int ioaddr; in ungermann_try_io_port() local
308 for (ioaddr = 0x300; ioaddr < 0x3e0; ioaddr += 0x20) { in ungermann_try_io_port()
331 unsigned int ioaddr; in fmvj18x_config() local
441 ioaddr = dev->base_addr; in fmvj18x_config()
590 unsigned int ioaddr; in fmvj18x_setup_mfc() local
719 unsigned int ioaddr; in fjn_interrupt() local
788 htons(inw(ioaddr + 0)), htons(inw(ioaddr + 2)), in fjn_tx_timeout()
789 htons(inw(ioaddr + 4)), htons(inw(ioaddr + 6)), in fjn_tx_timeout()
790 htons(inw(ioaddr + 8)), htons(inw(ioaddr + 10)), in fjn_tx_timeout()
791 htons(inw(ioaddr + 12)), htons(inw(ioaddr + 14))); in fjn_tx_timeout()
[all …]
/drivers/net/ethernet/dec/tulip/
A Dpnic.c22 void __iomem *ioaddr = tp->base_addr; in pnic_do_nway() local
23 u32 phy_reg = ioread32(ioaddr + 0xB8); in pnic_do_nway()
35 iowrite32(0x1F868, ioaddr + 0xB8); in pnic_do_nway()
55 void __iomem *ioaddr = tp->base_addr; in pnic_lnk_change() local
62 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkFail) | TPLnkPass, ioaddr + CSR7); in pnic_lnk_change()
71 iowrite32(0x30, ioaddr + CSR12); in pnic_lnk_change()
83 iowrite32((ioread32(ioaddr + CSR7) & ~TPLnkPass) | TPLnkFail, ioaddr + CSR7); in pnic_lnk_change()
94 if(!ioread32(ioaddr + CSR7)) { in pnic_timer()
129 ioread32(ioaddr + CSR5), in pnic_timer()
130 ioread32(ioaddr + 0xB8)); in pnic_timer()
[all …]

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