Searched refs:irq_enable_mask (Results 1 – 7 of 7) sorted by relevance
| /drivers/gpu/drm/i915/gt/ |
| A D | gen6_engine_cs.c | 428 ~(engine->irq_enable_mask | engine->irq_keep_mask)); in gen6_irq_enable()
433 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); in gen6_irq_enable()
439 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); in gen6_irq_disable()
444 ENGINE_WRITE(engine, RING_IMR, ~engine->irq_enable_mask); in hsw_irq_enable_vecs()
449 gen6_gt_pm_unmask_irq(engine->gt, engine->irq_enable_mask); in hsw_irq_enable_vecs()
455 gen6_gt_pm_mask_irq(engine->gt, engine->irq_enable_mask); in hsw_irq_disable_vecs()
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| A D | gen2_engine_cs.c | 295 engine->i915->irq_mask &= ~engine->irq_enable_mask; in gen2_irq_enable()
302 engine->i915->irq_mask |= engine->irq_enable_mask; in gen2_irq_disable()
308 gen5_gt_enable_irq(engine->gt, engine->irq_enable_mask); in gen5_irq_enable()
313 gen5_gt_disable_irq(engine->gt, engine->irq_enable_mask); in gen5_irq_disable()
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| A D | intel_ring_submission.c | 1205 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; in setup_rcs()
1220 engine->irq_enable_mask = I915_USER_INTERRUPT; in setup_rcs()
1236 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; in setup_vcs()
1245 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; in setup_vcs()
1247 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; in setup_vcs()
1256 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; in setup_bcs()
1271 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; in setup_vecs()
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| A D | intel_engine_types.h | 505 u32 irq_enable_mask; /* bitmask to enable ring interrupt */ member
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| A D | intel_execlists_submission.c | 3253 ~(engine->irq_enable_mask | engine->irq_keep_mask)); in gen8_logical_ring_enable_irq()
3503 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; in logical_ring_default_irqs()
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| /drivers/pinctrl/ |
| A D | pinctrl-single.c | 136 unsigned irq_enable_mask; member
701 if (pcs_soc->irq_enable_mask) { in pcs_add_pin()
705 if (val & pcs_soc->irq_enable_mask) { in pcs_add_pin()
708 val &= ~pcs_soc->irq_enable_mask; in pcs_add_pin()
1411 soc_mask = pcs_soc->irq_enable_mask; in pcs_irq_set()
1582 if (!pcs_soc->irq_enable_mask || in pcs_irq_init_chained_handler()
1937 .irq_enable_mask = (1 << 14), /* OMAP_WAKEUP_EN */
1942 .irq_enable_mask = (1 << 24), /* WAKEUPENABLE */
1948 .irq_enable_mask = (1 << 29), /* OMAP_WAKEUP_EN */
1954 .irq_enable_mask = (1 << 29), /* WKUP_EN */
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| /drivers/dma/ti/ |
| A D | omap-dma.c | 59 uint32_t irq_enable_mask; member
639 status &= od->irq_enable_mask; in omap_dma_irq()
732 od->irq_enable_mask |= val; in omap_dma_alloc_chan_resources()
733 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); in omap_dma_alloc_chan_resources()
767 od->irq_enable_mask &= ~BIT(c->dma_ch); in omap_dma_free_chan_resources()
768 omap_dma_glbl_write(od, IRQENABLE_L1, od->irq_enable_mask); in omap_dma_free_chan_resources()
1777 od->irq_enable_mask = 0; in omap_dma_probe()
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