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Searched refs:ix (Results 1 – 25 of 72) sorted by relevance

123

/drivers/hwmon/
A Ddme1737.c74 #define DME1737_REG_IN(ix) ((ix) < 5 ? 0x20 + (ix) : \ argument
115 #define DME1737_REG_PWM(ix) ((ix) < 3 ? 0x30 + (ix) \ argument
617 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { in dme1737_update_device()
634 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { in dme1737_update_device()
660 for (ix = 0; ix < ARRAY_SIZE(lsb); ix++) { in dme1737_update_device()
666 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { in dme1737_update_device()
672 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { in dme1737_update_device()
678 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) { in dme1737_update_device()
703 for (ix = 0; ix < ARRAY_SIZE(data->pwm); ix++) { in dme1737_update_device()
2214 for (ix = 0; ix < 3; ix++) { in dme1737_create_files()
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A Dvt1211.c62 #define VT1211_REG_IN(ix) (0x21 + (ix)) argument
63 #define VT1211_REG_IN_MIN(ix) ((ix) == 0 ? 0x3e : 0x2a + 2 * (ix)) argument
64 #define VT1211_REG_IN_MAX(ix) ((ix) == 0 ? 0x3d : 0x29 + 2 * (ix)) argument
72 #define VT1211_REG_FAN(ix) (0x29 + (ix)) argument
78 #define VT1211_REG_PWM(ix) (0x60 + (ix)) argument
254 for (ix = 0; ix < ARRAY_SIZE(data->in); ix++) { in vt1211_update_device()
266 for (ix = 0; ix < ARRAY_SIZE(data->temp); ix++) { in vt1211_update_device()
278 for (ix = 0; ix < ARRAY_SIZE(data->fan); ix++) { in vt1211_update_device()
306 for (ix = 0; ix < ARRAY_SIZE(data->pwm_auto_temp); ix++) { in vt1211_update_device()
346 res = IN_FROM_REG(ix, data->in[ix]); in show_in()
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/drivers/net/ethernet/mellanox/mlx5/core/en/
A Drx_res.c326 int ix; in mlx5e_rx_res_channels_init() local
338 for (ix = 0; ix < res->max_nch; ix++) { in mlx5e_rx_res_channels_init()
349 for (ix = 0; ix < res->max_nch; ix++) { in mlx5e_rx_res_channels_init()
422 unsigned int ix; in mlx5e_rx_res_channels_destroy() local
424 for (ix = 0; ix < res->max_nch; ix++) { in mlx5e_rx_res_channels_destroy()
560 for (ix = 0; ix < chs->num; ix++) { in mlx5e_rx_res_channels_activate()
572 for (ix = 0; ix < nch; ix++) in mlx5e_rx_res_channels_activate()
591 unsigned int ix; in mlx5e_rx_res_channels_deactivate() local
596 for (ix = 0; ix < res->rss_nch; ix++) in mlx5e_rx_res_channels_deactivate()
641 for (ix = 0; ix < MLX5E_MAX_NUM_RSS; ix++) { in mlx5e_rx_res_packet_merge_set_param()
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A Dchannels.c14 static struct mlx5e_channel *mlx5e_channels_get(struct mlx5e_channels *chs, unsigned int ix) in mlx5e_channels_get() argument
16 WARN_ON_ONCE(ix >= mlx5e_channels_get_num(chs)); in mlx5e_channels_get()
17 return chs->c[ix]; in mlx5e_channels_get()
20 bool mlx5e_channels_is_xsk(struct mlx5e_channels *chs, unsigned int ix) in mlx5e_channels_is_xsk() argument
22 struct mlx5e_channel *c = mlx5e_channels_get(chs, ix); in mlx5e_channels_is_xsk()
27 void mlx5e_channels_get_regular_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn, in mlx5e_channels_get_regular_rqn() argument
30 struct mlx5e_channel *c = mlx5e_channels_get(chs, ix); in mlx5e_channels_get_regular_rqn()
37 void mlx5e_channels_get_xsk_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn, in mlx5e_channels_get_xsk_rqn() argument
40 struct mlx5e_channel *c = mlx5e_channels_get(chs, ix); in mlx5e_channels_get_xsk_rqn()
A Dfs_tt_redirect.c148 int ix = 0; in fs_udp_create_groups() local
178 MLX5_SET_CFG(in, start_flow_index, ix); in fs_udp_create_groups()
179 ix += MLX5E_FS_UDP_GROUP1_SIZE; in fs_udp_create_groups()
180 MLX5_SET_CFG(in, end_flow_index, ix - 1); in fs_udp_create_groups()
188 MLX5_SET_CFG(in, start_flow_index, ix); in fs_udp_create_groups()
189 ix += MLX5E_FS_UDP_GROUP2_SIZE; in fs_udp_create_groups()
430 int ix = 0; in fs_any_create_groups() local
449 MLX5_SET_CFG(in, start_flow_index, ix); in fs_any_create_groups()
450 ix += MLX5E_FS_ANY_GROUP1_SIZE; in fs_any_create_groups()
459 MLX5_SET_CFG(in, start_flow_index, ix); in fs_any_create_groups()
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A Drqt.c118 unsigned int ix = i; in mlx5e_calc_indir_rqns() local
121 ix = mlx5e_bits_invert(ix, ilog2(indir->actual_table_size)); in mlx5e_calc_indir_rqns()
123 ix = indir->table[ix]; in mlx5e_calc_indir_rqns()
125 if (WARN_ON(ix >= num_rqns)) in mlx5e_calc_indir_rqns()
130 rss_rqns[i] = rqns[ix]; in mlx5e_calc_indir_rqns()
132 rss_vhca_ids[i] = vhca_ids[ix]; in mlx5e_calc_indir_rqns()
A Dchannels.h12 bool mlx5e_channels_is_xsk(struct mlx5e_channels *chs, unsigned int ix);
13 void mlx5e_channels_get_regular_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn,
15 void mlx5e_channels_get_xsk_rqn(struct mlx5e_channels *chs, unsigned int ix, u32 *rqn,
A Dqos.c59 int ix; in mlx5e_get_qos_sq() local
61 ix = qid % params->num_channels; in mlx5e_get_qos_sq()
63 c = priv->channels.c[ix]; in mlx5e_get_qos_sq()
76 int txq_ix, ix, qid, err = 0; in mlx5e_open_qos_sq() local
112 ix = node_qid % params->num_channels; in mlx5e_open_qos_sq()
114 c = chs->c[ix]; in mlx5e_open_qos_sq()
217 int ix; in mlx5e_close_qos_sq() local
221 ix = qid % params->num_channels; in mlx5e_close_qos_sq()
223 c = priv->channels.c[ix]; in mlx5e_close_qos_sq()
341 u16 qid = params->num_channels * i + c->ix; in mlx5e_qos_deactivate_queues()
/drivers/net/ethernet/mellanox/mlx5/core/en/xsk/
A Dpool.c54 xsk->pools[ix] = pool; in mlx5e_xsk_add_pool()
60 xsk->pools[ix] = NULL; in mlx5e_xsk_remove_pool()
79 struct xsk_buff_pool *pool, u16 ix) in mlx5e_xsk_enable_locked() argument
96 err = mlx5e_xsk_add_pool(&priv->xsk, pool, ix); in mlx5e_xsk_enable_locked()
123 c = priv->channels.c[ix]; in mlx5e_xsk_enable_locked()
144 mlx5e_xsk_remove_pool(&priv->xsk, ix); in mlx5e_xsk_enable_locked()
166 &priv->xsk, ix); in mlx5e_xsk_disable_locked()
179 c = priv->channels.c[ix]; in mlx5e_xsk_disable_locked()
191 mlx5e_xsk_remove_pool(&priv->xsk, ix); in mlx5e_xsk_disable_locked()
198 u16 ix) in mlx5e_xsk_enable_pool() argument
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A Drx.c19 int mlx5e_xsk_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix) in mlx5e_xsk_alloc_rx_mpwqe() argument
21 struct mlx5e_mpw_info *wi = mlx5e_get_mpw_info(rq, ix); in mlx5e_xsk_alloc_rx_mpwqe()
130 offset = ix * rq->mpwqe.mtts_per_wqe; in mlx5e_xsk_alloc_rx_mpwqe()
160 int mlx5e_xsk_alloc_rx_wqes_batched(struct mlx5e_rq *rq, u16 ix, int wqe_bulk) in mlx5e_xsk_alloc_rx_wqes_batched() argument
171 contig = mlx5_wq_cyc_get_size(wq) - ix; in mlx5e_xsk_alloc_rx_wqes_batched()
173 alloc = xsk_buff_alloc_batch(rq->xsk_pool, buffs + ix, wqe_bulk); in mlx5e_xsk_alloc_rx_wqes_batched()
175 alloc = xsk_buff_alloc_batch(rq->xsk_pool, buffs + ix, contig); in mlx5e_xsk_alloc_rx_wqes_batched()
181 int j = mlx5_wq_cyc_ctr2ix(wq, ix + i); in mlx5e_xsk_alloc_rx_wqes_batched()
198 int mlx5e_xsk_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, int wqe_bulk) in mlx5e_xsk_alloc_rx_wqes() argument
204 int j = mlx5_wq_cyc_ctr2ix(wq, ix + i); in mlx5e_xsk_alloc_rx_wqes()
A Dpool.h10 struct mlx5e_xsk *xsk, u16 ix) in mlx5e_xsk_get_pool() argument
15 if (unlikely(ix >= params->num_channels)) in mlx5e_xsk_get_pool()
18 return xsk->pools[ix]; in mlx5e_xsk_get_pool()
A Drx.h11 int mlx5e_xsk_alloc_rx_mpwqe(struct mlx5e_rq *rq, u16 ix);
12 int mlx5e_xsk_alloc_rx_wqes_batched(struct mlx5e_rq *rq, u16 ix, int wqe_bulk);
13 int mlx5e_xsk_alloc_rx_wqes(struct mlx5e_rq *rq, u16 ix, int wqe_bulk);
/drivers/net/ethernet/mellanox/mlx5/core/
A Dwq.h82 void mlx5_wq_cyc_wqe_dump(struct mlx5_wq_cyc *wq, u16 ix, u8 nstrides);
157 static inline void *mlx5_wq_cyc_get_wqe(struct mlx5_wq_cyc *wq, u16 ix) in mlx5_wq_cyc_get_wqe() argument
159 return mlx5_frag_buf_get_wqe(&wq->fbc, ix); in mlx5_wq_cyc_get_wqe()
164 return mlx5_frag_buf_get_idx_last_contig_stride(&wq->fbc, ix) - ix + 1; in mlx5_wq_cyc_get_contig_wqebbs()
202 struct mlx5_cqe64 *cqe = mlx5_frag_buf_get_wqe(&wq->fbc, ix); in mlx5_cqwq_get_wqe()
283 static inline void *mlx5_wq_ll_get_wqe(struct mlx5_wq_ll *wq, u16 ix) in mlx5_wq_ll_get_wqe() argument
285 return mlx5_frag_buf_get_wqe(&wq->fbc, ix); in mlx5_wq_ll_get_wqe()
288 static inline u16 mlx5_wq_ll_get_wqe_next_ix(struct mlx5_wq_ll *wq, u16 ix) in mlx5_wq_ll_get_wqe_next_ix() argument
290 struct mlx5_wqe_srq_next_seg *wqe = mlx5_wq_ll_get_wqe(wq, ix); in mlx5_wq_ll_get_wqe_next_ix()
302 static inline void mlx5_wq_ll_pop(struct mlx5_wq_ll *wq, __be16 ix, in mlx5_wq_ll_pop() argument
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A Den_fs.c117 int ix = mlx5e_hash_l2(addr); in mlx5e_add_l2_to_hash() local
1019 int ix = 0; in mlx5e_create_l2_table_groups() local
1041 ix += MLX5E_L2_GROUP1_SIZE; in mlx5e_create_l2_table_groups()
1052 ix += MLX5E_L2_GROUP2_SIZE; in mlx5e_create_l2_table_groups()
1062 ix += MLX5E_L2_GROUP_TRAP_SIZE; in mlx5e_create_l2_table_groups()
1136 int ix = 0; in __mlx5e_create_vlan_table_groups() local
1144 ix += MLX5E_VLAN_GROUP0_SIZE; in __mlx5e_create_vlan_table_groups()
1156 ix += MLX5E_VLAN_GROUP1_SIZE; in __mlx5e_create_vlan_table_groups()
1167 ix += MLX5E_VLAN_GROUP2_SIZE; in __mlx5e_create_vlan_table_groups()
1178 ix += MLX5E_VLAN_GROUP3_SIZE; in __mlx5e_create_vlan_table_groups()
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/drivers/net/ethernet/mellanox/mlx5/core/lib/
A Dfs_ttc.c393 int ix = 0; in mlx5_create_ttc_table_groups() local
418 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_groups()
431 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_groups()
433 MLX5_SET_CFG(in, end_flow_index, ix - 1); in mlx5_create_ttc_table_groups()
441 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_groups()
451 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_ttc_table_groups()
557 int ix = 0; in mlx5_create_inner_ttc_table_groups() local
579 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_inner_ttc_table_groups()
592 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_inner_ttc_table_groups()
602 MLX5_SET_CFG(in, start_flow_index, ix); in mlx5_create_inner_ttc_table_groups()
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A Dipsec_fs_roce.c343 int ix = 0; in ipsec_fs_roce_tx_mpv_create_group_rules() local
351 MLX5_SET_CFG(in, start_flow_index, ix); in ipsec_fs_roce_tx_mpv_create_group_rules()
352 ix += MLX5_TX_ROCE_GROUP_SIZE; in ipsec_fs_roce_tx_mpv_create_group_rules()
448 int ix = 0; in ipsec_fs_roce_rx_mpv_create() local
506 MLX5_SET_CFG(in, start_flow_index, ix); in ipsec_fs_roce_rx_mpv_create()
507 ix += 1; in ipsec_fs_roce_rx_mpv_create()
605 int ix = 0; in mlx5_ipsec_fs_roce_tx_create() local
636 ix += MLX5_TX_ROCE_GROUP_SIZE; in mlx5_ipsec_fs_roce_tx_create()
716 int ix = 0; in mlx5_ipsec_fs_roce_rx_create() local
752 ix += MLX5_RX_ROCE_GROUP_SIZE; in mlx5_ipsec_fs_roce_rx_create()
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A Dmpfs.c79 static int alloc_l2table_index(struct mlx5_mpfs *l2table, u32 *ix) in alloc_l2table_index() argument
83 *ix = find_first_zero_bit(l2table->bitmap, l2table->size); in alloc_l2table_index()
84 if (*ix >= l2table->size) in alloc_l2table_index()
87 __set_bit(*ix, l2table->bitmap); in alloc_l2table_index()
92 static void free_l2table_index(struct mlx5_mpfs *l2table, u32 ix) in free_l2table_index() argument
94 __clear_bit(ix, l2table->bitmap); in free_l2table_index()
A Dmpfs.h53 int ix = MLX5_L2_ADDR_HASH(mac); \
57 hlist_for_each_entry(ptr, &(hash)[ix], node.hlist) \
68 int ix = MLX5_L2_ADDR_HASH(mac); \
74 hlist_add_head(&ptr->node.hlist, &(hash)[ix]);\
/drivers/media/dvb-frontends/
A Dmxl692.c203 for (ix = 0; ix < div_size; ix++) in mxl692_checksum()
215 u32 ix, temp; in mxl692_validate_fw_header() local
235 for (ix = 16; ix < buf_len; ix++) in mxl692_validate_fw_header()
255 ix = *index; in mxl692_write_fw_block()
258 total_len = buffer[ix + 1] << 16 | buffer[ix + 2] << 8 | buffer[ix + 3]; in mxl692_write_fw_block()
260 addr = buffer[ix + 4] << 24 | buffer[ix + 5] << 16 | in mxl692_write_fw_block()
261 buffer[ix + 6] << 8 | buffer[ix + 7]; in mxl692_write_fw_block()
289 *index = ix; in mxl692_write_fw_block()
416 u32 ix = 0; in mxl692_opread() local
426 for (ix = 0; ix < size; ix += 4) { in mxl692_opread()
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/drivers/input/misc/
A Dyealink.c284 int ix, len; in yealink_set_ringtone() local
300 ix = 0; in yealink_set_ringtone()
301 while (size != ix) { in yealink_set_ringtone()
302 len = size - ix; in yealink_set_ringtone()
309 ix += len; in yealink_set_ringtone()
319 int i, ix, len; in yealink_do_idle_tasks() local
321 ix = yld->stat_ix; in yealink_do_idle_tasks()
351 yld->copy.b[ix] = val; in yealink_do_idle_tasks()
354 switch(ix) { in yealink_do_idle_tasks()
387 ix++; in yealink_do_idle_tasks()
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/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dsmu_helper.h155 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
159 PHM_GET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
167 cgs_write_ind_register(device, port, ix##reg, \
168 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
172 cgs_write_ind_register(device, port, ix##reg, \
173 PHM_SET_FIELD(cgs_read_ind_register(device, port, ix##reg), \
181 PHM_WAIT_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
192 PHM_WAIT_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
206 PHM_WAIT_VFPF_INDIRECT_REGISTER_UNEQUAL_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
220 PHM_WAIT_VFPF_INDIRECT_REGISTER_GIVEN_INDEX(hwmgr, port, ix##reg, value, mask)
/drivers/net/ethernet/mellanox/mlx5/core/fpga/
A Dconn.c103 unsigned int ix; in mlx5_fpga_conn_post_recv() local
122 conn->qp.rq.bufs[ix] = buf; in mlx5_fpga_conn_post_recv()
146 unsigned int ix, sgi; in mlx5_fpga_conn_post_send() local
171 conn->qp.sq.bufs[ix] = buf; in mlx5_fpga_conn_post_send()
254 int ix, err; in mlx5_fpga_conn_rq_cqe() local
257 buf = conn->qp.rq.bufs[ix]; in mlx5_fpga_conn_rq_cqe()
295 int ix; in mlx5_fpga_conn_sq_cqe() local
607 int ix; in mlx5_fpga_conn_free_recv_bufs() local
609 for (ix = 0; ix < conn->qp.rq.size; ix++) { in mlx5_fpga_conn_free_recv_bufs()
621 int ix; in mlx5_fpga_conn_flush_send_bufs() local
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/drivers/net/wireless/marvell/mwifiex/
A Dutil.c801 int ix; in mwifiex_hist_data_reset() local
805 for (ix = 0; ix < MWIFIEX_MAX_AC_RX_RATES; ix++) in mwifiex_hist_data_reset()
806 atomic_set(&phist_data->rx_rate[ix], 0); in mwifiex_hist_data_reset()
807 for (ix = 0; ix < MWIFIEX_MAX_SNR; ix++) in mwifiex_hist_data_reset()
808 atomic_set(&phist_data->snr[ix], 0); in mwifiex_hist_data_reset()
809 for (ix = 0; ix < MWIFIEX_MAX_NOISE_FLR; ix++) in mwifiex_hist_data_reset()
810 atomic_set(&phist_data->noise_flr[ix], 0); in mwifiex_hist_data_reset()
811 for (ix = 0; ix < MWIFIEX_MAX_SIG_STRENGTH; ix++) in mwifiex_hist_data_reset()
812 atomic_set(&phist_data->sig_str[ix], 0); in mwifiex_hist_data_reset()
/drivers/gpu/drm/radeon/
A Dtrinity_dpm.c541 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_divider_value() local
568 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_ds_dividers() local
580 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_ss_dividers() local
593 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_vid() local
610 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_allos_gnb_slow() local
622 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_force_nbp_state() local
634 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_display_wm() local
646 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_vce_wm() local
658 u32 ix = index * TRINITY_SIZEOF_DPM_STATE_TABLE; in trinity_set_at() local
663 WREG32_SMC(SMU_SCLK_DPM_STATE_0_AT + ix, value); in trinity_set_at()
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/drivers/net/ethernet/mellanox/mlx5/core/esw/
A Dqos.c83 u32 ix; member
230 &node->ix); in esw_qos_node_create_sched_element()
246 node->ix); in esw_qos_node_destroy_sched_element()
285 node->ix, in esw_qos_sched_elem_config()
530 node->ix = tsar_ix; in __esw_qos_alloc_node()
893 node->ix = curr_ix; in esw_qos_tc_arbiter_scheduling_setup()
1353 &node->ix); in esw_qos_switch_tc_arbiter_node_to_vports()
1389 node->ix); in esw_qos_switch_vports_node_to_tc_arbiter()
1507 node->ix = curr_node->ix; in esw_qos_node_enable_tc_arbitration()
2032 node->ix); in esw_qos_vports_node_update_parent()
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