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/drivers/gpu/drm/amd/amdgpu/
A Damdgpu_jpeg.c89 if (adev->jpeg.reg_list) in amdgpu_jpeg_sw_fini()
316 if (!adev->jpeg.ras) in amdgpu_jpeg_ras_sw_init()
319 ras = adev->jpeg.ras; in amdgpu_jpeg_ras_sw_init()
364 mask = (1ULL << (adev->jpeg.num_jpeg_inst * adev->jpeg.num_jpeg_rings)) - 1; in amdgpu_debugfs_jpeg_sched_mask_set()
415 if (!(adev->jpeg.num_jpeg_inst > 1) && !(adev->jpeg.num_jpeg_rings > 1)) in amdgpu_debugfs_jpeg_sched_mask_init()
463 adev->jpeg.ip_dump = kcalloc(adev->jpeg.num_jpeg_inst * count, in amdgpu_jpeg_reg_dump_init()
465 if (!adev->jpeg.ip_dump) { in amdgpu_jpeg_reg_dump_init()
470 adev->jpeg.reg_list = reg; in amdgpu_jpeg_reg_dump_init()
480 adev->jpeg.reg_count = 0; in amdgpu_jpeg_reg_dump_fini()
489 if (!adev->jpeg.ip_dump) in amdgpu_jpeg_dump_ip_state()
[all …]
A Djpeg_v2_5.c79 adev->jpeg.num_jpeg_rings = 1; in jpeg_v2_5_early_init()
84 adev->jpeg.harvest_config |= 1 << i; in jpeg_v2_5_early_init()
111 if (adev->jpeg.harvest_config & (1 << i)) in jpeg_v2_5_sw_init()
145 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v2_5_sw_init()
170 adev->jpeg.supported_reset = in jpeg_v2_5_sw_init()
218 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v2_5_hw_init()
586 if (state == adev->jpeg.cur_state) in jpeg_v2_5_set_powergating_state()
595 adev->jpeg.cur_state = state; in jpeg_v2_5_set_powergating_state()
766 adev->jpeg.inst[i].ring_dec->me = i; in jpeg_v2_5_set_dec_ring_funcs()
788 adev->jpeg.inst[i].irq.num_types = 1; in jpeg_v2_5_set_irq_funcs()
[all …]
A Djpeg_v5_0_1.c118 if (!adev->jpeg.num_jpeg_inst || adev->jpeg.num_jpeg_inst > AMDGPU_MAX_JPEG_INSTANCES) in jpeg_v5_0_1_early_init()
173 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v5_0_1_sw_init()
191 adev->jpeg.internal.jpeg_pitch[j] = in jpeg_v5_0_1_sw_init()
203 adev->jpeg.supported_reset = in jpeg_v5_0_1_sw_init()
268 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v5_0_1_hw_init()
272 adev->jpeg.inst[i].aid_id); in jpeg_v5_0_1_hw_init()
718 if (state == adev->jpeg.cur_state) in jpeg_v5_0_1_set_powergating_state()
727 adev->jpeg.cur_state = state; in jpeg_v5_0_1_set_powergating_state()
909 adev->jpeg.inst[i].aid_id = in jpeg_v5_0_1_set_dec_ring_funcs()
929 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; in jpeg_v5_0_1_set_irq_funcs()
[all …]
A Djpeg_v4_0_5.c91 adev->jpeg.num_jpeg_inst = 1; in jpeg_v4_0_5_early_init()
94 adev->jpeg.num_jpeg_inst = 2; in jpeg_v4_0_5_early_init()
103 adev->jpeg.num_jpeg_rings = 1; in jpeg_v4_0_5_early_init()
159 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v4_0_5_sw_init()
177 adev->jpeg.supported_reset = in jpeg_v4_0_5_sw_init()
231 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v4_0_5_hw_init()
513 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v4_0_5_start()
720 if (state == adev->jpeg.cur_state) in jpeg_v4_0_5_set_powergating_state()
729 adev->jpeg.cur_state = state; in jpeg_v4_0_5_set_powergating_state()
844 adev->jpeg.inst[i].ring_dec->me = i; in jpeg_v4_0_5_set_dec_ring_funcs()
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A Djpeg_v4_0_3.c176 ring = &adev->jpeg.inst[i].ring_dec[j]; in jpeg_v4_0_3_sw_init()
199 adev->jpeg.internal.jpeg_pitch[j] = in jpeg_v4_0_3_sw_init()
219 adev->jpeg.supported_reset = in jpeg_v4_0_3_sw_init()
399 ring = adev->jpeg.inst[i].ring_dec; in jpeg_v4_0_3_hw_init()
406 adev->jpeg.inst[i].aid_id); in jpeg_v4_0_3_hw_init()
1035 if (state == adev->jpeg.cur_state) in jpeg_v4_0_3_set_powergating_state()
1044 adev->jpeg.cur_state = state; in jpeg_v4_0_3_set_powergating_state()
1075 if (adev->jpeg.inst[inst].aid_id == i) in jpeg_v4_0_3_process_interrupt()
1217 adev->jpeg.inst[i].aid_id = in jpeg_v4_0_3_set_dec_ring_funcs()
1237 adev->jpeg.inst->irq.num_types += adev->jpeg.num_jpeg_rings; in jpeg_v4_0_3_set_irq_funcs()
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A Djpeg_v4_0.c75 adev->jpeg.num_jpeg_inst = 1; in jpeg_v4_0_early_init()
76 adev->jpeg.num_jpeg_rings = 1; in jpeg_v4_0_early_init()
124 ring = adev->jpeg.inst->ring_dec; in jpeg_v4_0_sw_init()
146 adev->jpeg.supported_reset = in jpeg_v4_0_sw_init()
224 cancel_delayed_work_sync(&adev->jpeg.idle_work); in jpeg_v4_0_hw_fini()
472 ring = adev->jpeg.inst->ring_dec; in jpeg_v4_0_start_sriov()
681 adev->jpeg.cur_state = AMD_PG_STATE_UNGATE; in jpeg_v4_0_set_powergating_state()
685 if (state == adev->jpeg.cur_state) in jpeg_v4_0_set_powergating_state()
694 adev->jpeg.cur_state = state; in jpeg_v4_0_set_powergating_state()
806 adev->jpeg.inst->irq.num_types = 1; in jpeg_v4_0_set_irq_funcs()
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A Djpeg_v5_0_0.c69 adev->jpeg.num_jpeg_inst = 1; in jpeg_v5_0_0_early_init()
70 adev->jpeg.num_jpeg_rings = 1; in jpeg_v5_0_0_early_init()
105 ring = adev->jpeg.inst->ring_dec; in jpeg_v5_0_0_sw_init()
123 adev->jpeg.supported_reset = in jpeg_v5_0_0_sw_init()
191 cancel_delayed_work_sync(&adev->jpeg.idle_work); in jpeg_v5_0_0_hw_fini()
193 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v5_0_0_hw_fini()
354 adev->jpeg.inst[inst_idx].dpg_sram_curr_addr = in jpeg_v5_0_0_start_dpg_mode()
606 if (state == adev->jpeg.cur_state) in jpeg_v5_0_0_set_powergating_state()
615 adev->jpeg.cur_state = state; in jpeg_v5_0_0_set_powergating_state()
636 amdgpu_fence_process(adev->jpeg.inst->ring_dec); in jpeg_v5_0_0_process_interrupt()
[all …]
A Djpeg_v3_0.c82 adev->jpeg.num_jpeg_inst = 1; in jpeg_v3_0_early_init()
83 adev->jpeg.num_jpeg_rings = 1; in jpeg_v3_0_early_init()
106 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v3_0_sw_init()
118 ring = adev->jpeg.inst->ring_dec; in jpeg_v3_0_sw_init()
135 adev->jpeg.supported_reset = in jpeg_v3_0_sw_init()
195 cancel_delayed_work_sync(&adev->jpeg.idle_work); in jpeg_v3_0_hw_fini()
197 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v3_0_hw_fini()
520 if(state == adev->jpeg.cur_state) in jpeg_v3_0_set_powergating_state()
529 adev->jpeg.cur_state = state; in jpeg_v3_0_set_powergating_state()
550 amdgpu_fence_process(adev->jpeg.inst->ring_dec); in jpeg_v3_0_process_interrupt()
[all …]
A Djpeg_v2_0.c68 adev->jpeg.num_jpeg_inst = 1; in jpeg_v2_0_early_init()
69 adev->jpeg.num_jpeg_rings = 1; in jpeg_v2_0_early_init()
92 VCN_2_0__SRCID__JPEG_DECODE, &adev->jpeg.inst->irq); in jpeg_v2_0_sw_init()
104 ring = adev->jpeg.inst->ring_dec; in jpeg_v2_0_sw_init()
121 adev->jpeg.supported_reset = in jpeg_v2_0_sw_init()
181 cancel_delayed_work_sync(&adev->jpeg.idle_work); in jpeg_v2_0_hw_fini()
183 if (adev->jpeg.cur_state != AMD_PG_STATE_GATE && in jpeg_v2_0_hw_fini()
729 if (state == adev->jpeg.cur_state) in jpeg_v2_0_set_powergating_state()
738 adev->jpeg.cur_state = state; in jpeg_v2_0_set_powergating_state()
759 amdgpu_fence_process(adev->jpeg.inst->ring_dec); in jpeg_v2_0_process_interrupt()
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A Djpeg_v1_0.c447 amdgpu_fence_process(adev->jpeg.inst->ring_dec); in jpeg_v1_0_process_interrupt()
469 adev->jpeg.num_jpeg_inst = 1; in jpeg_v1_0_early_init()
470 adev->jpeg.num_jpeg_rings = 1; in jpeg_v1_0_early_init()
491 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->jpeg.inst->irq); in jpeg_v1_0_sw_init()
495 ring = adev->jpeg.inst->ring_dec; in jpeg_v1_0_sw_init()
498 r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst->irq, in jpeg_v1_0_sw_init()
503 adev->jpeg.internal.jpeg_pitch[0] = adev->jpeg.inst->external.jpeg_pitch[0] = in jpeg_v1_0_sw_init()
520 amdgpu_ring_fini(adev->jpeg.inst->ring_dec); in jpeg_v1_0_sw_fini()
533 struct amdgpu_ring *ring = adev->jpeg.inst->ring_dec; in jpeg_v1_0_start()
591 adev->jpeg.inst->ring_dec->funcs = &jpeg_v1_0_decode_ring_vm_funcs; in jpeg_v1_0_set_dec_ring_funcs()
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A Damdgpu_jpeg.h48 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
50 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = \
91 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = offset; \
92 *adev->jpeg.inst[inst_idx].dpg_sram_curr_addr++ = value; \
A Dvcn_v1_0.c264 ring = adev->jpeg.inst->ring_dec; in vcn_v1_0_hw_init()
1305 new_state->fw_based, new_state->jpeg); in vcn_v1_0_pause_dpg_mode()
1357 if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) { in vcn_v1_0_pause_dpg_mode()
1361 new_state->fw_based, new_state->jpeg); in vcn_v1_0_pause_dpg_mode()
1388 ring = adev->jpeg.inst->ring_dec; in vcn_v1_0_pause_dpg_mode()
1414 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg; in vcn_v1_0_pause_dpg_mode()
1889 new_state.jpeg = VCN_DPG_STATE__PAUSE; in vcn_v1_0_idle_work_handler()
1891 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; in vcn_v1_0_idle_work_handler()
1951 new_state.jpeg = VCN_DPG_STATE__PAUSE; in vcn_v1_0_set_pg_for_begin_use()
1953 new_state.jpeg = VCN_DPG_STATE__UNPAUSE; in vcn_v1_0_set_pg_for_begin_use()
[all …]
A Daqua_vanjaram.c287 max_res[AMDGPU_XCP_RES_JPEG] = adev->jpeg.num_jpeg_inst; in aqua_vanjaram_get_xcp_res_info()
305 adev->jpeg.num_jpeg_rings : xcp_cfg->xcp_res[i].num_inst; in aqua_vanjaram_get_xcp_res_info()
561 adev->jpeg.harvest_config = 0; in aqua_vanjaram_init_soc_config()
562 adev->jpeg.num_inst_per_aid = 1; in aqua_vanjaram_init_soc_config()
563 adev->jpeg.num_jpeg_inst = hweight32(adev->jpeg.inst_mask); in aqua_vanjaram_init_soc_config()
/drivers/media/platform/mediatek/jpeg/
A Dmtk_jpeg_core.c216 struct mtk_jpeg_dev *jpeg = ctx->jpeg; in mtk_jpeg_enum_fmt_vid_cap() local
227 struct mtk_jpeg_dev *jpeg = ctx->jpeg; in mtk_jpeg_enum_fmt_vid_out() local
309 struct mtk_jpeg_dev *jpeg = ctx->jpeg; in mtk_jpeg_g_fmt_vid_mplane() local
355 struct mtk_jpeg_dev *jpeg = ctx->jpeg; in mtk_jpeg_try_fmt_vid_cap_mplane() local
384 struct mtk_jpeg_dev *jpeg = ctx->jpeg; in mtk_jpeg_try_fmt_vid_out_mplane() local
415 struct mtk_jpeg_dev *jpeg = ctx->jpeg; in mtk_jpeg_s_fmt_mplane() local
680 struct mtk_jpeg_dev *jpeg = ctx->jpeg; in mtk_jpeg_queue_setup() local
734 struct mtk_jpeg_dev *jpeg = ctx->jpeg; in mtk_jpeg_check_resolution_change() local
1177 ctx->jpeg = jpeg; in mtk_jpeg_open()
1374 jpeg->vdev->lock = &jpeg->lock; in mtk_jpeg_probe()
[all …]
A Dmtk_jpeg_enc_hw.c216 ctx = jpeg->hw_param.curr_ctx; in mtk_jpegenc_put_buf()
222 dst_buffer = jpeg->hw_param.dst_buffer; in mtk_jpegenc_put_buf()
284 struct mtk_jpegenc_comp_dev *jpeg = priv; in mtk_jpegenc_hw_irq_handler() local
287 cancel_delayed_work(&jpeg->job_timeout_work); in mtk_jpegenc_hw_irq_handler()
289 ctx = jpeg->hw_param.curr_ctx; in mtk_jpegenc_hw_irq_handler()
290 src_buf = jpeg->hw_param.src_buffer; in mtk_jpegenc_hw_irq_handler()
291 dst_buf = jpeg->hw_param.dst_buffer; in mtk_jpegenc_hw_irq_handler()
302 ctx->jpeg->variant->support_34bit); in mtk_jpegenc_hw_irq_handler()
306 mtk_jpegenc_put_buf(jpeg); in mtk_jpegenc_hw_irq_handler()
307 pm_runtime_put(ctx->jpeg->dev); in mtk_jpegenc_hw_irq_handler()
[all …]
A DMakefile3 mtk-jpeg-enc-hw.o \
4 mtk-jpeg-dec-hw.o
9 mtk-jpeg-enc-hw-y := mtk_jpeg_enc_hw.o
10 mtk-jpeg-dec-hw-y := mtk_jpeg_dec_hw.o
A Dmtk_jpeg_dec_hw.c488 ctx = jpeg->hw_param.curr_ctx; in mtk_jpegdec_put_buf()
494 dst_buffer = jpeg->hw_param.dst_buffer; in mtk_jpegdec_put_buf()
555 struct mtk_jpegdec_comp_dev *jpeg = priv; in mtk_jpegdec_hw_irq_handler() local
558 cancel_delayed_work(&jpeg->job_timeout_work); in mtk_jpegdec_hw_irq_handler()
560 ctx = jpeg->hw_param.curr_ctx; in mtk_jpegdec_hw_irq_handler()
561 src_buf = jpeg->hw_param.src_buffer; in mtk_jpegdec_hw_irq_handler()
562 dst_buf = jpeg->hw_param.dst_buffer; in mtk_jpegdec_hw_irq_handler()
568 mtk_jpeg_dec_reset(jpeg->reg_base); in mtk_jpegdec_hw_irq_handler()
582 mtk_jpegdec_put_buf(jpeg); in mtk_jpegdec_hw_irq_handler()
583 pm_runtime_put(ctx->jpeg->dev); in mtk_jpegdec_hw_irq_handler()
[all …]
A DKconfig12 Mediatek jpeg codec driver provides HW capability to decode
16 module will be called mtk-jpeg
/drivers/media/platform/samsung/s5p-jpeg/
A Djpeg-core.c767 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_parse_decode_h_tbl() local
807 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_parse_huff_tbl() local
866 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_parse_decode_q_tbl() local
897 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_parse_q_tbl() local
971 ctx->jpeg = jpeg; in s5p_jpeg_open()
1856 struct s5p_jpeg *jpeg = ctx->jpeg; in s5p_jpeg_g_volatile_ctrl() local
2035 struct s5p_jpeg *jpeg = ctx->jpeg; in s5p_jpeg_device_run() local
2115 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_set_img_addr() local
2153 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_set_jpeg_addr() local
2196 struct s5p_jpeg *jpeg = ctx->jpeg; in exynos4_jpeg_device_run() local
[all …]
A DMakefile2 s5p-jpeg-objs := jpeg-core.o jpeg-hw-exynos3250.o jpeg-hw-exynos4.o jpeg-hw-s5p.o
3 obj-$(CONFIG_VIDEO_SAMSUNG_S5P_JPEG) += s5p-jpeg.o
/drivers/media/platform/nxp/imx-jpeg/
A Dmxc-jpeg.c809 dma_free_coherent(jpeg->dev, jpeg->slot_data.cfg_dec_size, in mxc_jpeg_free_slot_data()
856 jpeg->slot_data.cfg_dec_vaddr = dma_alloc_coherent(jpeg->dev, in mxc_jpeg_alloc_slot_data()
2808 jpeg->pd_dev = devm_kmalloc_array(dev, jpeg->num_domains, in mxc_jpeg_attach_pm_domains()
2813 jpeg->pd_link = devm_kmalloc_array(dev, jpeg->num_domains, in mxc_jpeg_attach_pm_domains()
2825 jpeg->pd_link[i] = device_link_add(dev, jpeg->pd_dev[i], in mxc_jpeg_attach_pm_domains()
2855 if (!jpeg) in mxc_jpeg_probe()
2889 jpeg->dev = dev; in mxc_jpeg_probe()
2939 jpeg->dec_vdev->v4l2_dev = &jpeg->v4l2_dev; in mxc_jpeg_probe()
2943 video_set_drvdata(jpeg->dec_vdev, jpeg); in mxc_jpeg_probe()
2994 ret = clk_bulk_prepare_enable(jpeg->num_clks, jpeg->clks); in mxc_jpeg_runtime_resume()
[all …]
A DMakefile2 mxc-jpeg-encdec-objs := mxc-jpeg-hw.o mxc-jpeg.o
3 obj-$(CONFIG_VIDEO_IMX8_JPEG) += mxc-jpeg-encdec.o
/drivers/media/platform/imagination/
A DMakefile2 e5010_jpeg_enc-objs := e5010-jpeg-enc-hw.o e5010-jpeg-enc.o
/drivers/media/platform/mediatek/
A DMakefile2 obj-y += jpeg/
/drivers/media/platform/samsung/
A DMakefile6 obj-y += s5p-jpeg/

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