Home
last modified time | relevance | path

Searched refs:khz (Results 1 – 25 of 28) sorted by relevance

12

/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
A Dnv40.c47 u32 ref = 27000, khz = 0; in read_pll_1() local
50 khz = ref * N / M; in read_pll_1()
52 return khz >> P; in read_pll_1()
66 u32 ref = 27000, khz = 0; in read_pll_2() local
69 khz = ref * N1 / M1; in read_pll_2()
72 khz = khz * N2 / M2; in read_pll_2()
74 khz = 0; in read_pll_2()
78 return khz >> P; in read_pll_2()
124 nv40_clk_calc_pll(struct nv40_clk *clk, u32 reg, u32 khz, in nv40_clk_calc_pll() argument
135 if (khz < pll.vco1.max_freq) in nv40_clk_calc_pll()
[all …]
A Dgt215.c187 gt215_clk_info(struct nvkm_clk *base, int idx, u32 khz, in gt215_clk_info() argument
196 switch (khz) { in gt215_clk_info()
199 return khz; in gt215_clk_info()
202 return khz; in gt215_clk_info()
205 return khz; in gt215_clk_info()
208 sdiv = min((sclk * 2) / khz, (u32)65); in gt215_clk_info()
210 diff = ((khz + 3000) - oclk); in gt215_clk_info()
248 ret = gt215_clk_info(&clk->base, idx, khz, info); in gt215_pll_info()
249 diff = khz - ret; in gt215_pll_info()
263 ret = gt215_pll_calc(subdev, &limits, khz, &N, NULL, &M, &P); in gt215_pll_info()
[all …]
A Dbase.c287 int khz = pstate->base.domain[nv_clk_src_mem]; in nvkm_pstate_prog() local
289 ret = ram->func->calc(ram, khz); in nvkm_pstate_prog()
/drivers/cpufreq/
A Dpowernow-k6.c157 unsigned khz; in powernow_k6_cpu_init() local
163 khz = cpu_khz; in powernow_k6_cpu_init()
165 if (khz >= usual_frequency_table[i].freq - FREQ_RANGE && in powernow_k6_cpu_init()
166 khz <= usual_frequency_table[i].freq + FREQ_RANGE) { in powernow_k6_cpu_init()
167 khz = usual_frequency_table[i].freq; in powernow_k6_cpu_init()
184 khz); in powernow_k6_cpu_init()
201 busfreq = khz / max_multiplier; in powernow_k6_cpu_init()
A Dpxa2xx-cpufreq.c51 unsigned int khz; member
195 new_freq_cpu = pxa_freq_settings[idx].khz; in pxa_set_target()
242 pxa255_run_freq_table[i].frequency = pxa255_run_freqs[i].khz; in pxa_cpufreq_init()
250 pxa255_turbo_freqs[i].khz; in pxa_cpufreq_init()
259 freq = pxa27x_freqs[i].khz; in pxa_cpufreq_init()
A Dgx-suspmod.c217 static unsigned int gx_validate_speed(unsigned int khz, u8 *on_duration, in gx_validate_speed() argument
229 tmp_off = ((khz * i) / stock_freq) & 0xff; in gx_validate_speed()
234 if (abs(tmp_freq - khz) <= abs(old_tmp_freq - khz)) { in gx_validate_speed()
250 static void gx_set_cpuspeed(struct cpufreq_policy *policy, unsigned int khz) in gx_set_cpuspeed() argument
259 new_khz = gx_validate_speed(khz, &gx_params->on_duration, in gx_set_cpuspeed()
A Dlonghaul.c110 int khz; in calc_speed() local
111 khz = (mult/10)*fsb; in calc_speed()
113 khz += fsb/2; in calc_speed()
114 khz *= 1000; in calc_speed()
115 return khz; in calc_speed()
A Dsa1110-cpufreq.c122 static inline u_int ns_to_cycles(u_int ns, u_int khz) in ns_to_cycles() argument
124 return (ns * khz + 999999) / 1000000; in ns_to_cycles()
A Dpowernow-k8.c1120 unsigned int khz = 0; in powernowk8_get() local
1130 khz = find_khz_freq_from_fid(data->currfid); in powernowk8_get()
1134 return khz; in powernowk8_get()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dclk_mgr_internal.h454 static inline int khz_to_mhz_ceil(int khz) in khz_to_mhz_ceil() argument
456 return (khz + 999) / 1000; in khz_to_mhz_ceil()
459 static inline int khz_to_mhz_floor(int khz) in khz_to_mhz_floor() argument
461 return khz / 1000; in khz_to_mhz_floor()
/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/
A Dbase.c38 nvkm_devinit_pll_set(struct nvkm_devinit *init, u32 type, u32 khz) in nvkm_devinit_pll_set() argument
40 return init->func->pll_set(init, type, khz); in nvkm_devinit_pll_set()
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
A Dnv50.c1030 struct nvkm_ior *ior, int id, u32 khz) in nv50_disp_super_ied_on() argument
1069 data = nvbios_oclk_match(bios, iedtrs.clkcmp[id], khz); in nv50_disp_super_ied_on()
1072 id, ior->asy.proto_evo, flags, khz); in nv50_disp_super_ied_on()
1160 const u32 khz = head->asy.hz / 1000; in nv50_disp_super_2_2_dp() local
1172 do_div(h, khz); in nv50_disp_super_2_2_dp()
1178 do_div(v, khz); in nv50_disp_super_2_2_dp()
1265 const u32 khz = head->asy.hz / 1000; in nv50_disp_super_2_2() local
1292 nv50_disp_super_ied_on(head, ior, 0, khz); in nv50_disp_super_2_2()
1311 const u32 khz = head->asy.hz / 1000; in nv50_disp_super_2_1() local
1312 HEAD_DBG(head, "supervisor 2.1 - %d khz", khz); in nv50_disp_super_2_1()
[all …]
A Dgm200.c71 gm200_sor_hdmi_scdc(struct nvkm_ior *ior, u32 khz, bool support, bool scrambling, in gm200_sor_hdmi_scdc() argument
78 ior->tmds.high_speed = khz > 340000; in gm200_sor_hdmi_scdc()
A Dior.h73 void (*scdc)(struct nvkm_ior *, u32 khz, bool support, bool scrambling,
/drivers/gpu/drm/sprd/
A Dmegacores_pll.c32 const u32 khz = 1000; in dphy_calc_pll_param() local
38 pll->potential_fvco = pll->freq / khz; in dphy_calc_pll_param()
39 pll->ref_clk = PHY_REF_CLK / khz; in dphy_calc_pll_param()
/drivers/gpu/drm/nouveau/nvif/
A Doutp.c227 u32 khz, bool scdc, bool scdc_scrambling, bool scdc_low_rates) in nvif_outp_hdmi() argument
237 args.khz = khz; in nvif_outp_hdmi()
246 args.head, args.enable, args.max_ac_packet, args.rekey, args.khz, in nvif_outp_hdmi()
/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
A Ddisp.c166 nvbios_oclk_match(struct nvkm_bios *bios, u16 cmp, u32 khz) in nvbios_oclk_match() argument
169 if (khz / 10 >= nvbios_rd16(bios, cmp + 0x00)) in nvbios_oclk_match()
/drivers/gpu/drm/nouveau/include/nvkm/subdev/
A Ddevinit.h15 int nvkm_devinit_pll_set(struct nvkm_devinit *, u32 type, u32 khz);
/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
A Ddisp.h40 u16 nvbios_oclk_match(struct nvkm_bios *, u16 cmp, u32 khz);
/drivers/gpu/drm/nouveau/
A Dnouveau_encoder.h159 bool nouveau_dp_train(struct nouveau_encoder *, bool mst, u32 khz, u8 bpc);
A Dnouveau_dp.c405 nouveau_dp_train(struct nouveau_encoder *outp, bool mst, u32 khz, u8 bpc) in nouveau_dp_train() argument
416 min_rate = DIV_ROUND_UP(khz * bpc * 3, 8); in nouveau_dp_train()
/drivers/ata/
A Dpata_legacy.c489 int khz[4] = { 50000, 40000, 33000, 25000 }; in opti82c611a_set_piomode() local
498 clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; in opti82c611a_set_piomode()
564 int khz[4] = { 50000, 40000, 33000, 25000 }; in opti82c46x_set_piomode() local
577 clock = 1000000000 / khz[sysclk]; in opti82c46x_set_piomode()
/drivers/gpu/drm/nouveau/include/nvif/
A Doutp.h92 int nvif_outp_hdmi(struct nvif_outp *, int head, bool enable, u8 max_ac_packet, u8 rekey, u32 khz,
A Dif0012.h178 __u32 khz; member
/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
A Dramgk104.c962 gk104_ram_calc_data(struct gk104_ram *ram, u32 khz, struct nvkm_ram_data *data) in gk104_ram_calc_data() argument
966 u32 mhz = khz / 1000; in gk104_ram_calc_data()
972 data->freq = khz; in gk104_ram_calc_data()

Completed in 55 milliseconds

12