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Searched refs:l (Results 1 – 25 of 637) sorted by relevance

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/drivers/video/fbdev/omap2/omapfb/dss/
A Dpll.c244 u32 l; in dss_pll_write_config_type_a() local
246 l = 0; in dss_pll_write_config_type_a()
248 l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */ in dss_pll_write_config_type_a()
259 l = 0; in dss_pll_write_config_type_a()
276 l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */ in dss_pll_write_config_type_a()
282 l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */ in dss_pll_write_config_type_a()
335 u32 l; in dss_pll_write_config_type_b() local
337 l = 0; in dss_pll_write_config_type_b()
344 l = FLD_MOD(l, 0x1, 13, 13); /* PLL_REFEN */ in dss_pll_write_config_type_b()
351 l = FLD_MOD(l, 0x4, 3, 1); in dss_pll_write_config_type_b()
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_top/
A Ddml2_top_soc15.c250 l->mode_support_params.display_cfg = &l->next_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase()
302 l->mode_support_params.display_cfg = &l->cur_candidate_display_cfg; in dml2_top_optimization_perform_optimization_phase_1()
788 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_check_mode_supported()
811 l->dppm_map_mode_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_check_mode_supported()
843 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
854 l->mode_support_params.display_cfg = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
891 l->mcache_phase.display_config = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
917 l->uclk_pstate_phase.display_config = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
936 l->vmin_phase.display_config = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
964 l->stutter_phase.display_config = &l->base_display_config_with_meta; in dml2_top_soc15_build_mode_programming()
[all …]
/drivers/gpu/drm/omapdrm/dss/
A Dpll.c402 u32 l; in dss_pll_write_config_type_a() local
404 l = 0; in dss_pll_write_config_type_a()
406 l = FLD_MOD(l, 1, 0, 0); /* PLL_STOPMODE */ in dss_pll_write_config_type_a()
417 l = 0; in dss_pll_write_config_type_a()
434 l = FLD_MOD(l, f, 4, 1); /* PLL_FREQSEL */ in dss_pll_write_config_type_a()
440 l = FLD_MOD(l, 1, 13, 13); /* PLL_REFEN */ in dss_pll_write_config_type_a()
529 u32 l; in dss_pll_write_config_type_b() local
531 l = 0; in dss_pll_write_config_type_b()
538 l = FLD_MOD(l, 0x1, 13, 13); /* PLL_REFEN */ in dss_pll_write_config_type_b()
545 l = FLD_MOD(l, 0x4, 3, 1); in dss_pll_write_config_type_b()
[all …]
/drivers/md/
A Ddm-ima.c28 int l = strlen(*buf); in fix_separator_chars() local
31 for (i = 0; i < l; i++) in fix_separator_chars()
280 l = 0; in dm_ima_measure_on_table_load()
435 l += active_len; in dm_ima_measure_on_device_resume()
442 l++; in dm_ima_measure_on_device_resume()
459 l += capacity_len; in dm_ima_measure_on_device_resume()
536 l++; in dm_ima_measure_on_device_remove()
550 l++; in dm_ima_measure_on_device_remove()
571 l += 2; in dm_ima_measure_on_device_remove()
575 l += capacity_len; in dm_ima_measure_on_device_remove()
[all …]
/drivers/macintosh/
A Dwindfarm_smu_controls.c163 const char *l; in smu_fan_create() local
170 if (l == NULL) in smu_fan_create()
188 if (!strcmp(l, "Rear Fan 0") || !strcmp(l, "Rear Fan") || in smu_fan_create()
189 !strcmp(l, "Rear fan 0") || !strcmp(l, "Rear fan") || in smu_fan_create()
192 else if (!strcmp(l, "Rear Fan 1") || !strcmp(l, "Rear fan 1") || in smu_fan_create()
196 !strcmp(l, "Front fan 0") || !strcmp(l, "Front fan") || in smu_fan_create()
206 else if (!strcmp(l, "Slots Fan") || !strcmp(l, "Slots fan") || in smu_fan_create()
209 else if (!strcmp(l, "Drive Bay") || !strcmp(l, "Drive bay") || in smu_fan_create()
216 if (!strcmp(l, "System Fan") || !strcmp(l, "System fan")) in smu_fan_create()
218 else if (!strcmp(l, "CPU Fan") || !strcmp(l, "CPU fan")) in smu_fan_create()
[all …]
/drivers/video/fbdev/omap/
A Dsossi.c212 u32 l; in _set_timing() local
230 u32 l; in _set_bits_per_cycle() local
233 l &= ~0x3ff; in _set_bits_per_cycle()
240 u32 l; in _set_tearsync_mode() local
388 u32 l; in sossi_setup_tearsync() local
411 l |= vs << 3; in sossi_setup_tearsync()
412 l |= hs; in sossi_setup_tearsync()
414 l |= 1 << 29; in sossi_setup_tearsync()
418 l |= 1 << 28; in sossi_setup_tearsync()
562 u32 l, k; in sossi_init() local
[all …]
A Dlcdc.c85 u32 l; in set_load_mode() local
91 l |= 1 << 20; in set_load_mode()
94 l |= 2 << 20; in set_load_mode()
106 u32 l; in enable_controller() local
117 u32 l; in disable_controller_async() local
127 l &= ~mask; in disable_controller_async()
242 u32 l; in lcdc_irq_handler() local
462 u32 l; in setup_regs() local
497 l &= ~0xff; in setup_regs()
677 u32 l; in omap_lcdc_init() local
[all …]
/drivers/md/bcache/
A Dbset.h510 l->top_p = l->keys_p = l->inline_keys; in bch_keylist_init()
515 l->keys = k; in bch_keylist_init_single()
516 l->top = bkey_next(k); in bch_keylist_init_single()
521 l->top = bkey_next(l->top); in bch_keylist_push()
526 bkey_copy(l->top, k); in bch_keylist_add()
527 bch_keylist_push(l); in bch_keylist_add()
532 return l->top == l->keys; in bch_keylist_empty()
537 l->top = l->keys; in bch_keylist_reset()
542 if (l->keys_p != l->inline_keys) in bch_keylist_free()
543 kfree(l->keys_p); in bch_keylist_free()
[all …]
A Dextents.c44 return c ? c > 0 : l.k < r.k; in bch_key_sort_cmp()
577 return (l->ptr[KEY_PTRS(l)] + r->ptr[KEY_PTRS(r)]) & in merge_chksums()
582 struct bkey *l, in bch_extent_merge() argument
592 if (l->ptr[i] + MAKE_PTR(0, KEY_SIZE(l), 0) != r->ptr[i] || in bch_extent_merge()
600 SET_KEY_OFFSET(l, KEY_OFFSET(l) + USHRT_MAX - KEY_SIZE(l)); in bch_extent_merge()
603 bch_cut_front(l, r); in bch_extent_merge()
607 if (KEY_CSUM(l)) { in bch_extent_merge()
609 l->ptr[KEY_PTRS(l)] = merge_chksums(l, r); in bch_extent_merge()
611 SET_KEY_CSUM(l, 0); in bch_extent_merge()
614 SET_KEY_OFFSET(l, KEY_OFFSET(l) + KEY_SIZE(r)); in bch_extent_merge()
[all …]
/drivers/scsi/arm/
A Dqueue.c110 struct list_head *l; in __queue_add() local
118 l = queue->free.next; in __queue_add()
119 list_del(l); in __queue_add()
128 list_add(l, &queue->head); in __queue_add()
165 struct list_head *l; in queue_remove_exclude() local
214 struct list_head *l; in queue_remove_tgtluntag() local
241 struct list_head *l; in queue_remove_all_target() local
247 __queue_remove(queue, l); in queue_remove_all_target()
264 struct list_head *l; in queue_probetgtlun() local
290 struct list_head *l; in queue_remove_cmd() local
[all …]
/drivers/cpufreq/
A Dp4-clockmod.c54 u32 l, h; in cpufreq_p4_setdc() local
61 if (l & 0x01) in cpufreq_p4_setdc()
80 l = (l & ~14); in cpufreq_p4_setdc()
81 l = l | (1<<4) | ((newstate & 0x7)<<1); in cpufreq_p4_setdc()
208 u32 l, h; in cpufreq_p4_get() local
212 if (l & 0x10) { in cpufreq_p4_get()
213 l = l >> 1; in cpufreq_p4_get()
214 l &= 0x7; in cpufreq_p4_get()
216 l = DC_DISABLE; in cpufreq_p4_get()
218 if (l != DC_DISABLE) in cpufreq_p4_get()
[all …]
/drivers/gpu/drm/sun4i/
A Dsun4i_backend.h29 #define SUN4I_BACKEND_MODCTL_LAY_EN(l) BIT(8 + l) argument
43 #define SUN4I_BACKEND_LAYSIZE_REG(l) (0x810 + (0x4 * (l))) argument
47 #define SUN4I_BACKEND_LAYCOOR_REG(l) (0x820 + (0x4 * (l))) argument
51 #define SUN4I_BACKEND_LAYLINEWIDTH_REG(l) (0x840 + (0x4 * (l))) argument
53 #define SUN4I_BACKEND_LAYFB_L32ADD_REG(l) (0x850 + (0x4 * (l))) argument
56 #define SUN4I_BACKEND_LAYFB_H4ADD_MSK(l) GENMASK(3 + ((l) * 8), (l) * 8) argument
57 #define SUN4I_BACKEND_LAYFB_H4ADD(l, val) ((val) << ((l) * 8)) argument
66 #define SUN4I_BACKEND_ATTCTL_REG0(l) (0x890 + (0x4 * (l))) argument
77 #define SUN4I_BACKEND_ATTCTL_REG1(l) (0x8a0 + (0x4 * (l))) argument
/drivers/char/tpm/
A Dtpm_tis_core.h70 #define TPM_ACCESS(l) (0x0000 | ((l) << 12)) argument
71 #define TPM_INT_ENABLE(l) (0x0008 | ((l) << 12)) argument
72 #define TPM_INT_VECTOR(l) (0x000C | ((l) << 12)) argument
73 #define TPM_INT_STATUS(l) (0x0010 | ((l) << 12)) argument
74 #define TPM_INTF_CAPS(l) (0x0014 | ((l) << 12)) argument
75 #define TPM_STS(l) (0x0018 | ((l) << 12)) argument
76 #define TPM_STS3(l) (0x001b | ((l) << 12)) argument
77 #define TPM_DATA_FIFO(l) (0x0024 | ((l) << 12)) argument
79 #define TPM_DID_VID(l) (0x0F00 | ((l) << 12)) argument
80 #define TPM_RID(l) (0x0F04 | ((l) << 12)) argument
/drivers/net/ethernet/smsc/
A Dsmc91x.h90 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, l) argument
91 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, l) argument
92 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) argument
93 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) argument
94 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) argument
95 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l) argument
130 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l) argument
131 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l) argument
132 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l) argument
161 #define SMC_insw(a, r, p, l) mcf_insw(a + r, p, l) argument
[all …]
/drivers/clocksource/
A Dtimer-ti-dm.c259 u32 l; in __omap_dm_timer_stop() local
263 l &= ~0x1; in __omap_dm_timer_stop()
706 u32 l; in omap_dm_timer_modify_idlect_mask() local
747 u32 l; in omap_dm_timer_start() local
815 u32 l; in omap_dm_timer_set_match() local
845 u32 l; in omap_dm_timer_set_pwm() local
878 u32 l; in omap_dm_timer_get_pwm_status() local
893 return l; in omap_dm_timer_get_pwm_status()
902 u32 l; in omap_dm_timer_set_prescaler() local
960 u32 l = mask; in omap_dm_timer_set_int_disable() local
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/drivers/isdn/capi/
A Dcapiutil.c196 #define structTLcpy(x, y, l) memcpy(x, y, l) argument
197 #define structTLcpyovl(x, y, l) memmove(x, y, l) argument
202 #define structTRcpy(x, y, l) memcpy(y, x, l) argument
203 #define structTRcpyovl(x, y, l) memmove(y, x, l) argument
484 cmsg->l++; in protocol_message_2_pars()
488 cmsg->l += 2; in protocol_message_2_pars()
502 cmsg->l += 1 + cmsg->m[cmsg->l]; in protocol_message_2_pars()
504 cmsg->l += 3 + *(u16 *) (cmsg->m + cmsg->l + 1); in protocol_message_2_pars()
512 cmsg->l++; in protocol_message_2_pars()
518 cmsg->l = (cmsg->m + _l)[0] == 255 ? cmsg->l + 3 : cmsg->l + 1; in protocol_message_2_pars()
[all …]
/drivers/media/platform/verisilicon/
A Dhantro_vp9.c74 return &cnts->count_coeffs[j][k][l][m]; in get_coeffs_arr()
77 return &cnts->count_coeffs8x8[j][k][l][m]; in get_coeffs_arr()
91 return &cnts->count_coeffs[j][k][l][m][3]; in get_eobs1()
108 vp9_ctx->cnts.coeff[i][j][k][l][m] = \
109 get_coeffs_arr(cnts, i, j, k, l, m); \
110 vp9_ctx->cnts.eob[i][j][k][l][m][0] = \
111 &cnts->count_eobs[i][j][k][l][m]; \
112 vp9_ctx->cnts.eob[i][j][k][l][m][1] = \
113 get_eobs1(cnts, i, j, k, l, m); \
121 int i, j, k, l, m; in init_v4l2_vp9_count_tbl() local
[all …]
/drivers/soundwire/
A Dgeneric_bandwidth_allocation.c192 int port_bo, i, l; in _sdw_compute_port_params() local
196 for (l = 0; l < SDW_MAX_LANES; l++) { in _sdw_compute_port_params()
197 if (l > 0 && !bus->lane_used_bandwidth[l]) in _sdw_compute_port_params()
231 int i, l, column_needed; in sdw_compute_group_params() local
267 for (l = 0; l < SDW_MAX_LANES; l++) { in sdw_compute_group_params()
268 if (l > 0 && !bus->lane_used_bandwidth[l]) in sdw_compute_group_params()
499 int l; in get_manager_lane() local
501 for (l = 1; l < SDW_MAX_LANES; l++) { in get_manager_lane()
619 for (l = 1; l < SDW_MAX_LANES; l++) { in sdw_compute_bus_params()
622 s_p_rt->lane = l; in sdw_compute_bus_params()
[all …]
/drivers/firmware/efi/
A Defibc.c42 unsigned long l; in efibc_reboot_notifier_call() local
54 for (l = 0; l < MAX_DATA_LEN - 1 && str[l] != '\0'; l++) in efibc_reboot_notifier_call()
55 wdata[l] = str[l]; in efibc_reboot_notifier_call()
56 wdata[l] = L'\0'; in efibc_reboot_notifier_call()
58 efibc_set_variable(L"LoaderEntryOneShot", wdata, l); in efibc_reboot_notifier_call()
/drivers/spi/
A Dspi-omap2-mcspi.c209 u32 l, rw; in omap2_mcspi_set_dma_req() local
219 l |= rw; in omap2_mcspi_set_dma_req()
221 l &= ~rw; in omap2_mcspi_set_dma_req()
229 u32 l; in omap2_mcspi_set_enable() local
231 l = cs->chctrl0; in omap2_mcspi_set_enable()
236 cs->chctrl0 = l; in omap2_mcspi_set_enable()
245 u32 l; in omap2_mcspi_set_cs() local
283 u32 l; in omap2_mcspi_set_mode() local
456 u32 l; in omap2_mcspi_rx_dma() local
706 u32 l; in omap2_mcspi_txrx_pio() local
[all …]
/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/
A Ddml2_core_dcn4.c420 l->mode_support_ex_params.mode_lib = &core->clean_me_up.mode_lib; in core_dcn4_mode_support()
421 l->mode_support_ex_params.in_display_cfg = &l->svp_expanded_display_cfg; in core_dcn4_mode_support()
422 l->mode_support_ex_params.min_clk_table = in_out->min_clk_table; in core_dcn4_mode_support()
423 l->mode_support_ex_params.min_clk_index = in_out->min_clk_index; in core_dcn4_mode_support()
426 result = dml2_core_calcs_mode_support_ex(&l->mode_support_ex_params); in core_dcn4_mode_support()
464 for (i = 0; i < l->svp_expanded_display_cfg.num_planes; i++) { in core_dcn4_mode_support()
469 for (i = 0; i < l->svp_expanded_display_cfg.num_planes; i++) { in core_dcn4_mode_support()
474 switch (l->mode_support_ex_params.out_evaluation_info->ODMMode[i]) { in core_dcn4_mode_support()
556 l->mode_programming_ex_params.mode_lib = &core->clean_me_up.mode_lib; in core_dcn4_mode_programming()
557 l->mode_programming_ex_params.in_display_cfg = &l->svp_expanded_display_cfg; in core_dcn4_mode_programming()
[all …]
A Ddml2_core_dcn4_calcs.c1062 while (l->minDET <= l->max_minDET && l->minDET_pipe == 0) { in CalculateDETBufferSize()
1064 l->minDET_pipe = l->minDET; in CalculateDETBufferSize()
2462 l->l_p.mvmpg_width = &l->mvmpg_width_l; in calculate_mcache_setting()
2463 l->l_p.mvmpg_height = &l->mvmpg_height_l; in calculate_mcache_setting()
2498 l->c_p.mvmpg_width = &l->mvmpg_width_c; in calculate_mcache_setting()
2511 l->mvmpg_access_width_l = p->surf_vert ? l->mvmpg_height_l : l->mvmpg_width_l; in calculate_mcache_setting()
2522 l->luma_time_factor = (double)l->mvmpg_height_c / l->mvmpg_height_l * 2; in calculate_mcache_setting()
2524 l->luma_time_factor = (double)l->mvmpg_width_c / l->mvmpg_width_l * 2; in calculate_mcache_setting()
12379 l->htotal = l->timing->h_total; in rq_dlg_get_dlg_reg()
12380 l->hactive = l->timing->h_active; in rq_dlg_get_dlg_reg()
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/drivers/gpu/drm/nouveau/include/nvkm/core/
A Dsubdev.h73 #define nvkm_printk_ok(s,u,l) \ argument
74 ((CONFIG_NOUVEAU_DEBUG >= (l)) && ((s)->debug >= (l) || ((u) && (u)->debug >= (l))))
75 #define nvkm_printk___(s,u,l,p,f,a...) do { \ argument
76 if (nvkm_printk_ok((s), (u), (l))) { \
83 #define nvkm_printk__(s,l,p,f,a...) nvkm_printk___((s), (s), (l), p, f, ##a) argument
84 #define nvkm_printk_(s,l,p,f,a...) nvkm_printk__((s), (l), p, " "f, ##a) argument
85 #define nvkm_printk(s,l,p,f,a...) nvkm_printk_((s), NV_DBG_##l, p, f, ##a) argument
/drivers/net/ethernet/microchip/lan966x/
A Dlan966x_vcap_debugfs.c25 for (int l = 0; l < admin->lookups; ++l) { in lan966x_vcap_is1_port_keys() local
26 out->prf(out->dst, "\n Lookup %d: ", l); in lan966x_vcap_is1_port_keys()
28 val = lan_rd(lan966x, ANA_VCAP_S1_CFG(port->chip_port, l)); in lan966x_vcap_is1_port_keys()
142 for (int l = 0; l < admin->lookups; ++l) { in lan966x_vcap_is2_port_keys() local
143 out->prf(out->dst, "\n Lookup %d: ", l); in lan966x_vcap_is2_port_keys()
146 if (ANA_VCAP_S2_CFG_SNAP_DIS_GET(val) & (BIT(0) << l)) in lan966x_vcap_is2_port_keys()
152 if (ANA_VCAP_S2_CFG_OAM_DIS_GET(val) & (BIT(0) << l)) in lan966x_vcap_is2_port_keys()
158 if (ANA_VCAP_S2_CFG_ARP_DIS_GET(val) & (BIT(0) << l)) in lan966x_vcap_is2_port_keys()
164 if (ANA_VCAP_S2_CFG_IP_OTHER_DIS_GET(val) & (BIT(0) << l)) in lan966x_vcap_is2_port_keys()
170 if (ANA_VCAP_S2_CFG_IP_TCPUDP_DIS_GET(val) & (BIT(0) << l)) in lan966x_vcap_is2_port_keys()
[all …]
/drivers/thermal/intel/
A Dx86_pkg_temp_thermal.c128 u32 l, h, mask, shift, intr; in sys_set_trip_temp() local
142 &l, &h); in sys_set_trip_temp()
155 l &= ~mask; in sys_set_trip_temp()
161 l &= ~intr; in sys_set_trip_temp()
163 l |= val << shift; in sys_set_trip_temp()
164 l |= intr; in sys_set_trip_temp()
168 l, h); in sys_set_trip_temp()
186 u32 l, h; in enable_pkg_thres_interrupt() local
193 l |= THERM_INT_THRESHOLD0_ENABLE; in enable_pkg_thres_interrupt()
195 l |= THERM_INT_THRESHOLD1_ENABLE; in enable_pkg_thres_interrupt()
[all …]

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