Searched refs:lane_offset (Results 1 – 3 of 3) sorted by relevance
| /drivers/phy/freescale/ |
| A D | phy-fsl-lynx-28g.c | 241 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); in lynx_28g_cleanup_lane() local
248 LYNX_28G_PCCC_SXGMII_DIS << lane_offset, in lynx_28g_cleanup_lane()
249 GENMASK(3, 0) << lane_offset); in lynx_28g_cleanup_lane()
254 LYNX_28G_PCC8_SGMII_DIS << lane_offset, in lynx_28g_cleanup_lane()
255 GENMASK(3, 0) << lane_offset); in lynx_28g_cleanup_lane()
264 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); in lynx_28g_lane_set_sgmii() local
272 LYNX_28G_PCC8_SGMII << lane_offset, in lynx_28g_lane_set_sgmii()
273 GENMASK(3, 0) << lane_offset); in lynx_28g_lane_set_sgmii()
300 u32 lane_offset = LYNX_28G_LNa_PCC_OFFSET(lane); in lynx_28g_lane_set_10gbaser() local
308 LYNX_28G_PCCC_10GBASER << lane_offset, in lynx_28g_lane_set_10gbaser()
[all …]
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| /drivers/phy/qualcomm/ |
| A D | phy-qcom-uniphy-pcie-28lp.c | 58 int lane_offset; /* offset between the lane register bases */ member
126 .lane_offset = 0x800,
134 .lane_offset = 0x800,
154 base += data->lane_offset; in qcom_uniphy_pcie_init()
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| /drivers/gpu/drm/amd/amdkfd/ |
| A D | cwsr_trap_handler_gfx12.asm | 1063 function write_16sgpr_to_v2(s, lane_offset)
1066 v_writelane_b32 v2, s[sgpr_idx], sgpr_idx + lane_offset
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