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Searched refs:layer (Results 1 – 25 of 143) sorted by relevance

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/drivers/gpu/drm/xlnx/
A Dzynqmp_disp.c1005 zynqmp_disp_avbuf_enable_video(layer->disp, layer); in zynqmp_disp_layer_enable()
1006 zynqmp_disp_blend_layer_enable(layer->disp, layer); in zynqmp_disp_layer_enable()
1025 zynqmp_disp_avbuf_disable_video(layer->disp, layer); in zynqmp_disp_layer_disable()
1026 zynqmp_disp_blend_layer_disable(layer->disp, layer); in zynqmp_disp_layer_disable()
1047 layer->disp_fmt = zynqmp_disp_layer_find_format(layer, info->format); in zynqmp_disp_layer_set_format()
1052 zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); in zynqmp_disp_layer_set_format()
1089 layer->disp_fmt = zynqmp_disp_layer_find_live_format(layer, in zynqmp_disp_layer_set_live_format()
1094 zynqmp_disp_avbuf_set_format(layer->disp, layer, layer->disp_fmt); in zynqmp_disp_layer_set_live_format()
1096 layer->drm_fmt = drm_format_info(layer->disp_fmt->drm_fmt); in zynqmp_disp_layer_set_live_format()
1165 if (!layer->info) in zynqmp_disp_layer_release_dma()
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A Dzynqmp_disp.h53 u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer,
55 u32 *zynqmp_disp_live_layer_formats(struct zynqmp_disp_layer *layer,
57 void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer);
58 void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer);
59 void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,
61 void zynqmp_disp_layer_set_live_format(struct zynqmp_disp_layer *layer,
63 int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,
/drivers/net/ethernet/microchip/sparx5/
A Dsparx5_qos.c96 HSCH_HSCH_TIMER_CFG(layer, group)); in sparx5_lg_set_leak_time()
151 if (sparx5_lg_is_empty(sparx5, layer, group)) in sparx5_lg_is_singular()
176 if (sparx5_lg_is_empty(sparx5, layer, i)) in sparx5_lg_get_group_by_index()
200 struct sparx5_layer *l = &layers[layer]; in sparx5_lg_get_group_by_rate()
247 sparx5_lg_disable(sparx5, layer, group); in sparx5_lg_conf_set()
263 HSCH_HSCH_LEAK_CFG(layer, group)); in sparx5_lg_conf_set()
395 struct sparx5_layer *layer; in sparx5_leak_groups_init() local
404 layer = &layers[i]; in sparx5_leak_groups_init()
406 lg = &layer->leak_groups[ii]; in sparx5_leak_groups_init()
498 u32 layer, u32 idx) in sparx5_tc_tbf_add() argument
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A Dsparx5_tc.c64 u32 portno, u32 *layer, u32 *idx) in sparx5_tc_get_layer_and_idx() argument
67 *layer = 2; in sparx5_tc_get_layer_and_idx()
71 *layer = 0; in sparx5_tc_get_layer_and_idx()
91 u32 layer, se_idx; in sparx5_tc_setup_qdisc_tbf() local
94 &layer, &se_idx); in sparx5_tc_setup_qdisc_tbf()
98 return sparx5_tc_tbf_add(port, &qopt->replace_params, layer, in sparx5_tc_setup_qdisc_tbf()
101 return sparx5_tc_tbf_del(port, layer, se_idx); in sparx5_tc_setup_qdisc_tbf()
/drivers/media/dvb-frontends/
A Dmb86a20s.c552 switch (c->layer[layer].modulation) { in isdbt_layer_min_bitrate()
566 switch (c->layer[layer].fec) { in isdbt_layer_min_bitrate()
627 for (layer = 0; layer < NUM_LAYERS; layer++) { in mb86a20s_get_frontend()
635 c->layer[layer].segment_count = rc; in mb86a20s_get_frontend()
637 c->layer[layer].segment_count = 0; in mb86a20s_get_frontend()
647 c->layer[layer].modulation = rc; in mb86a20s_get_frontend()
653 c->layer[layer].fec = rc; in mb86a20s_get_frontend()
659 c->layer[layer].interleaving = rc; in mb86a20s_get_frontend()
1449 for (layer = 0; layer < NUM_LAYERS; layer++) { in mb86a20s_get_blk_error_layer_CNR()
1551 for (layer = 0; layer < NUM_LAYERS + 1; layer++) { in mb86a20s_stats_not_ready()
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A Ddib8000.c2394 nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count; in dib8000_set_isdbt_common_channel()
2399 nbseg_diff += (c->layer[i].modulation == DQPSK) * c->layer[i].segment_count; in dib8000_set_isdbt_common_channel()
2475 tmcc_pow += (((c->layer[i].modulation == DQPSK) * 4 + 1) * c->layer[i].segment_count) ; in dib8000_set_isdbt_common_channel()
2567 c->layer[0].fec = FEC_2_3; in dib8000_autosearch_start()
2603 c->layer[0].fec = FEC_2_3; in dib8000_autosearch_start()
3535 c->layer[i].fec = FEC_1_2; in dib8000_get_frontend()
3597 state->fe[index_frontend]->dtv_property_cache.layer[i].fec = c->layer[i].fec; in dib8000_get_frontend()
4021 if (layer >= 0) { in dib8000_get_time_us()
4022 ini_layer = layer; in dib8000_get_time_us()
4023 end_layer = layer + 1; in dib8000_get_time_us()
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A Dtc90522.c220 c->layer[0].fec = c->fec_inner; in tc90522s_get_frontend()
226 c->layer[1].fec = fec_conv_sat[v]; in tc90522s_get_frontend()
228 c->layer[1].segment_count = 0; in tc90522s_get_frontend()
235 c->layer[1].modulation = QPSK; in tc90522s_get_frontend()
362 c->layer[0].segment_count = 0; in tc90522t_get_frontend()
365 c->layer[0].segment_count = v; in tc90522t_get_frontend()
369 c->layer[0].interleaving = v; in tc90522t_get_frontend()
375 c->layer[1].segment_count = 0; in tc90522t_get_frontend()
378 c->layer[1].segment_count = v; in tc90522t_get_frontend()
387 c->layer[2].segment_count = 0; in tc90522t_get_frontend()
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/drivers/gpu/drm/logicvc/
A Dlogicvc_layer.c149 u32 index = layer->index; in logicvc_plane_atomic_update()
239 u32 index = layer->index; in logicvc_plane_atomic_disable()
439 return layer; in logicvc_layer_get_from_index()
451 return layer; in logicvc_layer_get_from_type()
473 layer = devm_kzalloc(dev, sizeof(*layer), GFP_KERNEL); in logicvc_layer_init()
474 if (!layer) { in logicvc_layer_init()
480 layer->index = index; in logicvc_layer_init()
551 if (layer) in logicvc_layer_init()
562 list_del(&layer->list); in logicvc_layer_fini()
563 devm_kfree(dev, layer); in logicvc_layer_fini()
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/drivers/gpu/drm/sun4i/
A Dsun4i_layer.c198 struct sun4i_layer *layer; in sun4i_layer_init_one() local
201 layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); in sun4i_layer_init_one()
202 if (!layer) in sun4i_layer_init_one()
205 layer->id = id; in sun4i_layer_init_one()
206 layer->backend = backend; in sun4i_layer_init_one()
228 drm_plane_create_zpos_property(&layer->plane, layer->id, in sun4i_layer_init_one()
231 return layer; in sun4i_layer_init_one()
249 struct sun4i_layer *layer; in sun4i_layers_init() local
252 if (IS_ERR(layer)) { in sun4i_layers_init()
255 return ERR_CAST(layer); in sun4i_layers_init()
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A Dsun8i_ui_layer.h17 #define SUN8I_MIXER_CHAN_UI_LAYER_ATTR(base, layer) \ argument
18 ((base) + 0x20 * (layer) + 0x0)
19 #define SUN8I_MIXER_CHAN_UI_LAYER_SIZE(base, layer) \ argument
20 ((base) + 0x20 * (layer) + 0x4)
21 #define SUN8I_MIXER_CHAN_UI_LAYER_COORD(base, layer) \ argument
22 ((base) + 0x20 * (layer) + 0x8)
23 #define SUN8I_MIXER_CHAN_UI_LAYER_PITCH(base, layer) \ argument
24 ((base) + 0x20 * (layer) + 0xc)
26 ((base) + 0x20 * (layer) + 0x10)
28 ((base) + 0x20 * (layer) + 0x14)
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A Dsun8i_ui_layer.c217 if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { in sun8i_ui_layer_atomic_check()
244 layer->overlay, plane); in sun8i_ui_layer_atomic_update()
246 layer->overlay, plane); in sun8i_ui_layer_atomic_update()
248 layer->overlay, plane); in sun8i_ui_layer_atomic_update()
299 struct sun8i_layer *layer; in sun8i_ui_layer_init_one() local
303 layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); in sun8i_ui_layer_init_one()
304 if (!layer) in sun8i_ui_layer_init_one()
337 layer->mixer = mixer; in sun8i_ui_layer_init_one()
339 layer->channel = channel; in sun8i_ui_layer_init_one()
340 layer->overlay = 0; in sun8i_ui_layer_init_one()
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A Dsun8i_vi_layer.h11 #define SUN8I_MIXER_CHAN_VI_LAYER_ATTR(base, layer) \ argument
12 ((base) + 0x30 * (layer) + 0x0)
13 #define SUN8I_MIXER_CHAN_VI_LAYER_SIZE(base, layer) \ argument
14 ((base) + 0x30 * (layer) + 0x4)
15 #define SUN8I_MIXER_CHAN_VI_LAYER_COORD(base, layer) \ argument
16 ((base) + 0x30 * (layer) + 0x8)
17 #define SUN8I_MIXER_CHAN_VI_LAYER_PITCH(base, layer, plane) \ argument
18 ((base) + 0x30 * (layer) + 0xc + 4 * (plane))
19 #define SUN8I_MIXER_CHAN_VI_LAYER_TOP_LADDR(base, layer, plane) \ argument
20 ((base) + 0x30 * (layer) + 0x18 + 4 * (plane))
A Dsun8i_csc.c143 static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, in sun8i_de3_ccsc_set_coefficients() argument
156 addr = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0); in sun8i_de3_ccsc_set_coefficients()
163 layer, in sun8i_de3_ccsc_set_coefficients()
167 layer, in sun8i_de3_ccsc_set_coefficients()
171 layer, i); in sun8i_de3_ccsc_set_coefficients()
197 mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer); in sun8i_de3_ccsc_enable()
208 void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, in sun8i_csc_set_ccsc_coefficients() argument
216 sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, layer, in sun8i_csc_set_ccsc_coefficients()
221 base = ccsc_base[mixer->cfg->ccsc][layer]; in sun8i_csc_set_ccsc_coefficients()
232 sun8i_de3_ccsc_enable(mixer->engine.regs, layer, enable); in sun8i_csc_enable_ccsc()
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A Dsun8i_vi_layer.c338 if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { in sun8i_vi_layer_atomic_check()
364 layer->overlay, plane); in sun8i_vi_layer_atomic_update()
366 layer->overlay, plane); in sun8i_vi_layer_atomic_update()
368 layer->overlay, plane); in sun8i_vi_layer_atomic_update()
480 struct sun8i_layer *layer; in sun8i_vi_layer_init_one() local
484 layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); in sun8i_vi_layer_init_one()
485 if (!layer) in sun8i_vi_layer_init_one()
546 layer->mixer = mixer; in sun8i_vi_layer_init_one()
548 layer->channel = index; in sun8i_vi_layer_init_one()
549 layer->overlay = 0; in sun8i_vi_layer_init_one()
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A Dsun4i_backend.c84 int layer, bool enable) in sun4i_backend_layer_enable() argument
89 layer); in sun4i_backend_layer_enable()
92 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer); in sun4i_backend_layer_enable()
268 SUN4I_BACKEND_ATTCTL_REG0(layer), in sun4i_backend_update_layer_formats()
283 SUN4I_BACKEND_ATTCTL_REG1(layer), in sun4i_backend_update_layer_formats()
290 int layer, uint32_t fmt) in sun4i_backend_update_layer_frontend() argument
302 SUN4I_BACKEND_ATTCTL_REG0(layer), in sun4i_backend_update_layer_frontend()
307 SUN4I_BACKEND_ATTCTL_REG1(layer), in sun4i_backend_update_layer_frontend()
375 layer, priority, pipe); in sun4i_backend_update_layer_zpos()
386 int layer) in sun4i_backend_cleanup_layer() argument
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A Dsun8i_mixer.c255 u32 ch_base = sun8i_channel_base(layer->mixer, layer->channel); in sun8i_layer_enable()
258 if (layer->type == SUN8I_LAYER_TYPE_UI) { in sun8i_layer_enable()
300 plane->base.id, layer->channel, layer->overlay, in sun8i_mixer_commit()
307 sun8i_layer_enable(layer, enable); in sun8i_mixer_commit()
340 struct sun8i_layer *layer; in sun8i_layers_init() local
343 if (IS_ERR(layer)) { in sun8i_layers_init()
346 return ERR_CAST(layer); in sun8i_layers_init()
349 planes[i] = &layer->plane; in sun8i_layers_init()
353 struct sun8i_layer *layer; in sun8i_layers_init() local
356 if (IS_ERR(layer)) { in sun8i_layers_init()
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A Dsun8i_ui_scaler.c130 void sun8i_ui_scaler_enable(struct sun8i_mixer *mixer, int layer, bool enable) in sun8i_ui_scaler_enable() argument
134 if (WARN_ON(layer < mixer->cfg->vi_num)) in sun8i_ui_scaler_enable()
137 base = sun8i_ui_scaler_base(mixer, layer); in sun8i_ui_scaler_enable()
148 void sun8i_ui_scaler_setup(struct sun8i_mixer *mixer, int layer, in sun8i_ui_scaler_setup() argument
156 if (WARN_ON(layer < mixer->cfg->vi_num)) in sun8i_ui_scaler_setup()
159 base = sun8i_ui_scaler_base(mixer, layer); in sun8i_ui_scaler_setup()
A Dsun4i_backend.h196 int layer, bool enable);
199 int layer, struct drm_plane *plane);
201 int layer, struct drm_plane *plane);
203 int layer, struct drm_plane *plane);
205 int layer, uint32_t in_fmt);
207 int layer, struct drm_plane *plane);
209 int layer);
/drivers/gpu/drm/atmel-hlcdc/
A Datmel_hlcdc_dc.h322 struct atmel_hlcdc_layer layer; member
334 return container_of(layer, struct atmel_hlcdc_plane, layer); in atmel_hlcdc_layer_to_plane()
438 regmap_write(layer->regmap, layer->desc->regs_offset + reg, val); in atmel_hlcdc_layer_write_reg()
446 regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val); in atmel_hlcdc_layer_read_reg()
454 atmel_hlcdc_layer_write_reg(layer, in atmel_hlcdc_layer_write_cfg()
455 layer->desc->cfgs_offset + in atmel_hlcdc_layer_write_cfg()
462 return atmel_hlcdc_layer_read_reg(layer, in atmel_hlcdc_layer_read_cfg()
463 layer->desc->cfgs_offset + in atmel_hlcdc_layer_read_cfg()
470 regmap_write(layer->regmap, in atmel_hlcdc_layer_write_clut()
479 layer->desc = desc; in atmel_hlcdc_layer_init()
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A Datmel_hlcdc_plane.c296 atmel_hlcdc_layer_write_cfg(&plane->layer, in atmel_hlcdc_plane_setup_scaler()
345 atmel_hlcdc_layer_write_cfg(&plane->layer, in atmel_xlcdc_plane_setup_scaler()
497 atmel_hlcdc_layer_write_cfg(&plane->layer, in atmel_hlcdc_plane_update_format()
529 atmel_hlcdc_layer_write_reg(&plane->layer, in atmel_hlcdc_update_buffers()
536 atmel_hlcdc_layer_write_reg(&plane->layer, in atmel_hlcdc_update_buffers()
539 atmel_hlcdc_layer_write_reg(&plane->layer, in atmel_hlcdc_update_buffers()
542 atmel_hlcdc_layer_write_reg(&plane->layer, in atmel_hlcdc_update_buffers()
551 atmel_hlcdc_layer_write_reg(&plane->layer, in atmel_xlcdc_update_buffers()
633 layout = &primary->layer.desc->layout; in atmel_hlcdc_plane_prepare_disc_area()
687 layout = &plane->layer.desc->layout; in atmel_hlcdc_plane_update_disc_area()
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/drivers/gpu/drm/arm/
A Dmalidp_planes.c483 if (!mp->layer->mmu_ctrl_offset) in malidp_de_prefetch_settings()
561 if (mp->layer->rot == ROTATE_NONE) in malidp_de_plane_check()
611 if (!mp->layer->stride_offset) in malidp_de_set_plane_pitches()
627 mp->layer->base + in malidp_de_set_plane_pitches()
628 mp->layer->stride_offset + i * 4); in malidp_de_set_plane_pitches()
681 plane->layer->base + plane->layer->yuv2rgb_offset + in malidp_de_set_color_encoding()
692 if (!mp->layer->mmu_ctrl_offset) in malidp_de_set_mmu_control()
701 mp->layer->base + mp->layer->mmu_ctrl_offset); in malidp_de_set_mmu_control()
748 if (!mp->layer->afbc_decoder_offset) in malidp_de_set_plane_afbc()
841 if (mp->layer->id == DE_SMART) { in malidp_de_plane_update()
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/drivers/gpu/drm/arm/display/komeda/
A Dkomeda_plane.c23 struct komeda_pipeline *pipe = kplane->layer->base.pipeline; in komeda_plane_init_data_flow()
57 komeda_complete_data_flow_cfg(kplane->layer, dflow, fb); in komeda_plane_init_data_flow()
78 struct komeda_layer *layer = kplane->layer; in komeda_plane_atomic_check() local
105 err = komeda_build_layer_split_data_flow(layer, in komeda_plane_atomic_check()
108 err = komeda_build_layer_data_flow(layer, in komeda_plane_atomic_check()
181 u32 layer_type = kplane->layer->layer_type; in komeda_plane_format_mod_supported()
241 struct komeda_layer *layer) in komeda_plane_add() argument
244 struct komeda_component *c = &layer->base; in komeda_plane_add()
255 kplane->layer = layer; in komeda_plane_add()
258 layer->layer_type, &n_formats); in komeda_plane_add()
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/drivers/net/ethernet/stmicro/stmmac/
A DKconfig78 This selects Ingenic SoCs glue layer support for the stmmac
121 This selects the Amlogic Meson SoC glue layer support for
165 This selects the Renesas RZ/N1 SoC glue layer support for
176 This selects NXP SoC glue layer support for the stmmac
192 This selects the Altera SOCFPGA SoC glue layer support
203 This selects the Sophgo SoC specific glue layer support
227 This selects STi SoC glue layer support for the stmmac
239 This selects STM32 SoC glue layer support for the stmmac
250 This selects Allwinner SoC glue layer support for the
262 This selects Allwinner SoC glue layer support for the
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/drivers/gpu/drm/tidss/
A Dtidss_crtc.c127 int layer; in tidss_crtc_position_planes() local
133 for (layer = 0; layer < tidss->feat->num_vids ; layer++) { in tidss_crtc_position_planes()
143 if (pstate->normalized_zpos == layer) { in tidss_crtc_position_planes()
155 layer); in tidss_crtc_position_planes()
157 dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer, in tidss_crtc_position_planes()
274 for (u32 layer = 0; layer < tidss->feat->num_vids; layer++) in tidss_crtc_atomic_disable() local
275 dispc_ovr_enable_layer(tidss->dispc, tcrtc->hw_videoport, layer, in tidss_crtc_atomic_disable()
/drivers/edac/
A Dedac_mc.c259 int layer; in edac_mc_alloc_dimms() local
294 for (layer = 0; layer < mci->n_layers; layer++) { in edac_mc_alloc_dimms()
296 edac_layer_name[mci->layers[layer].type], in edac_mc_alloc_dimms()
297 pos[layer]); in edac_mc_alloc_dimms()
300 dimm->location[layer] = pos[layer]; in edac_mc_alloc_dimms()
324 for (layer = mci->n_layers - 1; layer >= 0; layer--) { in edac_mc_alloc_dimms()
325 pos[layer]++; in edac_mc_alloc_dimms()
326 if (pos[layer] < mci->layers[layer].size) in edac_mc_alloc_dimms()
328 pos[layer] = 0; in edac_mc_alloc_dimms()
341 struct edac_mc_layer *layer; in edac_mc_alloc() local
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