Home
last modified time | relevance | path

Searched refs:limits (Results 1 – 25 of 187) sorted by relevance

12345678

/drivers/net/ipa/data/
A Dipa_data-v3.1.c190 .limits[IPA_RSRC_GROUP_SRC_UL] = {
193 .limits[IPA_RSRC_GROUP_SRC_DL] = {
207 .limits[IPA_RSRC_GROUP_SRC_UL] = {
210 .limits[IPA_RSRC_GROUP_SRC_DL] = {
224 .limits[IPA_RSRC_GROUP_SRC_UL] = {
227 .limits[IPA_RSRC_GROUP_SRC_DL] = {
241 .limits[IPA_RSRC_GROUP_SRC_UL] = {
244 .limits[IPA_RSRC_GROUP_SRC_DL] = {
258 .limits[IPA_RSRC_GROUP_SRC_UL] = {
261 .limits[IPA_RSRC_GROUP_SRC_DL] = {
[all …]
A Dipa_data-v5.0.c188 .limits[IPA_RSRC_GROUP_SRC_UL] = {
191 .limits[IPA_RSRC_GROUP_SRC_DL] = {
202 .limits[IPA_RSRC_GROUP_SRC_UL] = {
205 .limits[IPA_RSRC_GROUP_SRC_DL] = {
213 .limits[IPA_RSRC_GROUP_SRC_UL] = {
216 .limits[IPA_RSRC_GROUP_SRC_DL] = {
224 .limits[IPA_RSRC_GROUP_SRC_UL] = {
227 .limits[IPA_RSRC_GROUP_SRC_DL] = {
238 .limits[IPA_RSRC_GROUP_SRC_UL] = {
241 .limits[IPA_RSRC_GROUP_SRC_DL] = {
[all …]
A Dipa_data-v3.5.1.c182 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
185 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
193 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
196 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
204 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
207 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
215 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
218 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
229 .limits[IPA_RSRC_GROUP_SRC_LWA_DL] = {
232 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
[all …]
A Dipa_data-v5.5.c188 .limits[IPA_RSRC_GROUP_SRC_UL] = {
191 .limits[IPA_RSRC_GROUP_SRC_DL] = {
202 .limits[IPA_RSRC_GROUP_SRC_UL] = {
205 .limits[IPA_RSRC_GROUP_SRC_DL] = {
213 .limits[IPA_RSRC_GROUP_SRC_UL] = {
216 .limits[IPA_RSRC_GROUP_SRC_DL] = {
224 .limits[IPA_RSRC_GROUP_SRC_UL] = {
227 .limits[IPA_RSRC_GROUP_SRC_DL] = {
238 .limits[IPA_RSRC_GROUP_SRC_UL] = {
241 .limits[IPA_RSRC_GROUP_SRC_DL] = {
[all …]
A Dipa_data-v4.9.c176 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
179 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
187 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
190 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
201 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
212 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
223 .limits[IPA_RSRC_GROUP_SRC_DMA] = {
238 .limits[IPA_RSRC_GROUP_DST_DMA] = {
241 .limits[IPA_RSRC_GROUP_DST_UC] = {
252 .limits[IPA_RSRC_GROUP_DST_DMA] = {
[all …]
A Dipa_data-v4.5.c184 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
187 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
192 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
195 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
200 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
203 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
211 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
220 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
225 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
228 .limits[IPA_RSRC_GROUP_SRC_UC_RX_Q] = {
[all …]
A Dipa_data-v4.11.c175 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
180 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
185 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
190 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
195 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
204 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
207 .limits[IPA_RSRC_GROUP_DST_DRB_IP] = {
212 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
A Dipa_data-v4.2.c175 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
180 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
185 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
190 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
195 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
204 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
209 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = {
A Dipa_data-v4.7.c171 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
176 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
181 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
186 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
191 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = {
200 .limits[IPA_RSRC_GROUP_DST_UL_DL] = {
205 .limits[IPA_RSRC_GROUP_DST_UL_DL] = {
/drivers/media/i2c/
A Daptina-pll.c16 const struct aptina_pll_limits *limits, in aptina_pll_calculate() argument
29 if (pll->ext_clock < limits->ext_clock_min || in aptina_pll_calculate()
30 pll->ext_clock > limits->ext_clock_max) { in aptina_pll_calculate()
56 mf_min = max(mf_min, limits->out_clock_min / in aptina_pll_calculate()
58 mf_min = max(mf_min, limits->n_min * limits->p1_min / div); in aptina_pll_calculate()
59 mf_max = limits->m_max / pll->m; in aptina_pll_calculate()
62 mf_max = min(mf_max, DIV_ROUND_UP(limits->n_max * limits->p1_max, div)); in aptina_pll_calculate()
122 if (limits->p1_min == 0) { in aptina_pll_calculate()
127 p1_min = max(limits->p1_min, DIV_ROUND_UP(limits->out_clock_min * div, in aptina_pll_calculate()
129 p1_max = min(limits->p1_max, limits->out_clock_max * div / in aptina_pll_calculate()
[all …]
/drivers/net/ipa/
A Dipa_resource.c50 if (resource->limits[j].min || resource->limits[j].max) in ipa_resource_limits_valid()
63 if (resource->limits[j].min || resource->limits[j].max) in ipa_resource_limits_valid()
99 ylimits = group_count == 1 ? NULL : &resource->limits[1]; in ipa_resource_config_src()
101 &resource->limits[0], ylimits); in ipa_resource_config_src()
108 &resource->limits[2], ylimits); in ipa_resource_config_src()
115 &resource->limits[4], ylimits); in ipa_resource_config_src()
122 &resource->limits[6], ylimits); in ipa_resource_config_src()
138 &resource->limits[0], ylimits); in ipa_resource_config_dst()
145 &resource->limits[2], ylimits); in ipa_resource_config_dst()
152 &resource->limits[4], ylimits); in ipa_resource_config_dst()
[all …]
/drivers/infiniband/hw/mthca/
A Dmthca_main.c418 mdev->limits.reserved_mtts = ALIGN(mdev->limits.reserved_mtts * mdev->limits.mtt_seg_size, in mthca_init_icm()
422 mdev->limits.mtt_seg_size, in mthca_init_icm()
423 mdev->limits.num_mtt_segs, in mthca_init_icm()
434 mdev->limits.num_mpts, in mthca_init_icm()
445 mdev->limits.num_qps, in mthca_init_icm()
446 mdev->limits.reserved_qps, in mthca_init_icm()
456 mdev->limits.num_qps, in mthca_init_icm()
457 mdev->limits.reserved_qps, in mthca_init_icm()
467 mdev->limits.num_qps << in mthca_init_icm()
478 mdev->limits.num_cqs, in mthca_init_icm()
[all …]
A Dmthca_profile.c173 dev->limits.num_qps = profile[i].num; in mthca_make_profile()
178 dev->limits.num_eecs = profile[i].num; in mthca_make_profile()
183 dev->limits.num_srqs = profile[i].num; in mthca_make_profile()
188 dev->limits.num_cqs = profile[i].num; in mthca_make_profile()
199 dev->limits.num_eqs = profile[i].num; in mthca_make_profile()
212 dev->limits.num_mgms = profile[i].num >> 1; in mthca_make_profile()
220 dev->limits.num_mpts = profile[i].num; in mthca_make_profile()
226 dev->limits.num_mtt_segs = profile[i].num; in mthca_make_profile()
232 dev->limits.num_uars = profile[i].num; in mthca_make_profile()
255 dev->limits.num_pds = MTHCA_NUM_PDS; in mthca_make_profile()
[all …]
A Dmthca_mr.c339 BUG_ON(s % dev->limits.mtt_seg_size); in mthca_arbel_write_mtt_seg()
556 (dev->limits.num_mpts - 1)); in mthca_free_mr()
570 dev->limits.num_mpts, in mthca_init_mr_table()
577 dev->limits.fmr_reserved_mtts = 0; in mthca_init_mr_table()
593 if (dev->limits.fmr_reserved_mtts) { in mthca_init_mr_table()
603 mtts = dev->limits.num_mtt_segs; in mthca_init_mr_table()
604 mpts = dev->limits.num_mpts; in mthca_init_mr_table()
636 if (dev->limits.fmr_reserved_mtts) { in mthca_init_mr_table()
652 if (dev->limits.reserved_mtts) { in mthca_init_mr_table()
668 if (dev->limits.fmr_reserved_mtts) in mthca_init_mr_table()
[all …]
A Dmthca_provider.c90 props->max_qp = mdev->limits.num_qps - mdev->limits.reserved_qps; in mthca_query_device()
91 props->max_qp_wr = mdev->limits.max_wqes; in mthca_query_device()
92 props->max_send_sge = mdev->limits.max_sg; in mthca_query_device()
93 props->max_recv_sge = mdev->limits.max_sg; in mthca_query_device()
94 props->max_sge_rd = mdev->limits.max_sg; in mthca_query_device()
95 props->max_cq = mdev->limits.num_cqs - mdev->limits.reserved_cqs; in mthca_query_device()
96 props->max_cqe = mdev->limits.max_cqes; in mthca_query_device()
97 props->max_mr = mdev->limits.num_mpts - mdev->limits.reserved_mrws; in mthca_query_device()
98 props->max_pd = mdev->limits.num_pds - mdev->limits.reserved_pds; in mthca_query_device()
102 props->max_srq = mdev->limits.num_srqs - mdev->limits.reserved_srqs; in mthca_query_device()
[all …]
A Dmthca_srq.c215 if (attr->max_wr > dev->limits.max_srq_wqes || in mthca_alloc_srq()
216 attr->max_sge > dev->limits.max_srq_sge) in mthca_alloc_srq()
285 srq->srqn & (dev->limits.num_srqs - 1), in mthca_alloc_srq()
355 srq->srqn & (dev->limits.num_srqs - 1)); in mthca_free_srq()
645 return dev->limits.max_sg; in mthca_max_srq_sge()
661 return min_t(int, dev->limits.max_sg, in mthca_max_srq_sge()
662 ((1 << (fls(dev->limits.max_desc_sz) - 1)) - in mthca_max_srq_sge()
677 dev->limits.num_srqs, in mthca_init_srq_table()
678 dev->limits.num_srqs - 1, in mthca_init_srq_table()
679 dev->limits.reserved_srqs); in mthca_init_srq_table()
[all …]
/drivers/w1/masters/
A Dw1-uart.c107 const struct w1_uart_limits *limits, in w1_uart_set_config() argument
121 bits_low = to_ns(limits->bit_min_us) / bit_ns; in w1_uart_set_config()
125 if (low_ns < to_ns(limits->bit_min_us)) in w1_uart_set_config()
128 if (low_ns > to_ns(limits->bit_max_us)) in w1_uart_set_config()
132 if (limits->sample_us > 0 && in w1_uart_set_config()
139 if (to_ns(limits->cycle_us) > packet_ns) in w1_uart_set_config()
141 (to_ns(limits->cycle_us) - packet_ns) / NSEC_PER_USEC; in w1_uart_set_config()
159 struct w1_uart_limits limits = { .baudrate = 9600, in w1_uart_set_config_reset() local
165 of_property_read_u32(np, "reset-bps", &limits.baudrate); in w1_uart_set_config_reset()
180 struct w1_uart_limits limits = { .baudrate = 115200, in w1_uart_set_config_touch_0() local
[all …]
/drivers/gpu/drm/i915/display/
A Dintel_link_bw.c53 struct intel_link_bw_limits *limits) in intel_link_bw_init_limits() argument
58 limits->force_fec_pipes = 0; in intel_link_bw_init_limits()
59 limits->bpp_limit_reached_pipes = 0; in intel_link_bw_init_limits()
69 limits->force_fec_pipes |= BIT(pipe); in intel_link_bw_init_limits()
71 limits->max_bpp_x16[pipe] = INT_MAX; in intel_link_bw_init_limits()
75 limits->max_bpp_x16[pipe] = min(limits->max_bpp_x16[pipe], forced_bpp_x16); in intel_link_bw_init_limits()
100 struct intel_link_bw_limits *limits, in __intel_link_bw_reduce_bpp() argument
146 limits->max_bpp_x16[max_bpp_pipe] = max_bpp_x16 - 1; in __intel_link_bw_reduce_bpp()
153 struct intel_link_bw_limits *limits, in intel_link_bw_reduce_bpp() argument
212 struct intel_link_bw_limits *limits) in check_all_link_config() argument
[all …]
A Dintel_dp_mst.c472 max_bpp = limits->pipe.max_bpp; in mst_stream_dsc_compute_link_config()
473 min_bpp = limits->pipe.min_bpp; in mst_stream_dsc_compute_link_config()
588 drm_WARN_ON(display->drm, limits->min_rate != limits->max_rate); in adjust_limits_for_dsc_hblank_expansion_quirk()
590 if (limits->max_rate < 540000) in adjust_limits_for_dsc_hblank_expansion_quirk()
621 limits)) in mst_stream_compute_config_limits()
627 limits, in mst_stream_compute_config_limits()
673 conn_state, &limits); in mst_stream_compute_config()
696 &limits)) in mst_stream_compute_config()
712 conn_state, &limits); in mst_stream_compute_config()
717 conn_state, &limits, in mst_stream_compute_config()
[all …]
/drivers/clk/
A Dclk-axi-clkgen.c66 struct axi_clkgen_limits limits; member
152 d_max = min(fin / limits->fpfd_min, 80); in axi_clkgen_calc_params()
350 const struct axi_clkgen_limits *limits = &axi_clkgen->limits; in axi_clkgen_set_rate() local
399 const struct axi_clkgen_limits *limits = &axi_clkgen->limits; in axi_clkgen_determine_rate() local
516 axi_clkgen->limits.fpfd_min = 10000; in axi_clkgen_setup_limits()
517 axi_clkgen->limits.fvco_min = 600000; in axi_clkgen_setup_limits()
522 axi_clkgen->limits.fpfd_max = 450000; in axi_clkgen_setup_limits()
526 axi_clkgen->limits.fpfd_max = 500000; in axi_clkgen_setup_limits()
538 axi_clkgen->limits.fpfd_max = 550000; in axi_clkgen_setup_limits()
548 axi_clkgen->limits.fvco_min = 800000; in axi_clkgen_setup_limits()
[all …]
/drivers/video/fbdev/matrox/
A Dmatroxfb_misc.c544 minfo->limits.pixel.vcomax = maxdac; in parse_pins1()
556 minfo->limits.pixel.vcomax = 220000; in default_pins1()
565 minfo->limits.pixel.vcomax = in parse_pins2()
579 minfo->limits.pixel.vcomax = in default_pins2()
589 minfo->limits.pixel.vcomax = in parse_pins3()
607 minfo->limits.pixel.vcomax = in default_pins3()
638 minfo->limits.pixel.vcomax = in default_pins4()
691 minfo->limits.pixel.vcomax = in default_pins5()
692 minfo->limits.system.vcomax = in default_pins5()
694 minfo->limits.pixel.vcomin = in default_pins5()
[all …]
/drivers/md/
A Ddm-table.c234 struct queue_limits *limits = data; in device_area_is_invalid() local
423 struct queue_limits *limits = data; in dm_set_device_limits() local
438 limits->features |= (q->limits.features & BLK_FEAT_ATOMIC_WRITES); in dm_set_device_limits()
440 if (blk_stack_limits(limits, &q->limits, in dm_set_device_limits()
448 q->limits.alignment_offset, in dm_set_device_limits()
608 blk_set_stacking_limits(limits); in dm_set_stacking_limits()
679 limits->logical_block_size); in validate_hardware_logical_block_alignment()
1791 dm_set_stacking_limits(limits); in dm_calculate_queue_limits()
2064 limits->discard_granularity = 0; in dm_table_set_restrictions()
2065 limits->discard_alignment = 0; in dm_table_set_restrictions()
[all …]
/drivers/macintosh/
A Dtherm_adt746x.c80 u8 limits[3]; member
219 th->limits[0], th->limits[1], th->limits[2], in display_stats()
237 int var = th->temps[i] - th->limits[i]; in update_fans_speed()
314 th->limits[i] = default_limits_chip[i] + limit_adjust; in set_limit()
315 write_reg(th, LIMIT_REG[i], th->limits[i]); in set_limit()
318 th->limits[i] = default_limits_local[i] + limit_adjust; in set_limit()
378 BUILD_SHOW_FUNC_INT(sensor1_limit, th->limits[1])
379 BUILD_SHOW_FUNC_INT(sensor2_limit, th->limits[2])
535 th->initial_limits[2], th->limits[0], th->limits[1], in probe_thermostat()
536 th->limits[2]); in probe_thermostat()
[all …]
/drivers/clk/sophgo/
A Dclk-sg2044-pll.c73 const struct sg2044_pll_limit *limits; member
177 for_each_pll_limit_range(div2, &limits[PLL_LIMIT_POSTDIV2]) { in sg2042_pll_compute_postdiv()
178 for_each_pll_limit_range(div1, &limits[PLL_LIMIT_POSTDIV1]) { in sg2042_pll_compute_postdiv()
217 for_each_pll_limit_range(fbdiv, &limits[PLL_LIMIT_FBDIV]) { in sg2044_compute_pll_setting()
221 if (!sg2044_clk_fit_limit(vco, &limits[PLL_LIMIT_FOUTVCO])) in sg2044_compute_pll_setting()
224 ret = sg2042_pll_compute_postdiv(limits, in sg2044_compute_pll_setting()
269 pll->pll.limits[PLL_LIMIT_FOUT].max); in sg2044_pll_determine_rate()
271 ret = sg2044_compute_pll_setting(pll->pll.limits, target, in sg2044_pll_determine_rate()
344 ret = sg2044_compute_pll_setting(pll->pll.limits, rate, in sg2044_pll_set_rate()
409 .limits = (_limits), \
[all …]
/drivers/gpu/drm/exynos/
A Dexynos_drm_ipp.c244 if (copy_to_user((void __user *)ptr, format->limits, in exynos_drm_ipp_get_limits_ioctl()
245 sizeof(*format->limits) * format->num_limits)) in exynos_drm_ipp_get_limits_ioctl()
434 const struct drm_exynos_ipp_limit *l = limits; in __get_size_limit()
439 for (l = limits; l - limits < num_limits; l++) { in __get_size_limit()
484 if (!limits) in exynos_drm_ipp_check_size_limits()
496 __get_size_limit(limits, num_limits, id, &l); in exynos_drm_ipp_check_size_limits()
523 const struct drm_exynos_ipp_limit *limits, in exynos_drm_ipp_check_scale_limits() argument
529 for (; num_limits; limits++, num_limits--) in exynos_drm_ipp_check_scale_limits()
536 lh = (!swap) ? &limits->h : &limits->v; in exynos_drm_ipp_check_scale_limits()
537 lv = (!swap) ? &limits->v : &limits->h; in exynos_drm_ipp_check_scale_limits()
[all …]

Completed in 59 milliseconds

12345678