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Searched refs:link_bw (Results 1 – 25 of 27) sorted by relevance

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/drivers/gpu/drm/nouveau/
A Dnouveau_dp.c74 outp->dp.link_bw = 0; in nouveau_dp_probe_dpcd()
139 max_rate = min_t(int, max_rate, outp->dcb->dpconf.link_bw); in nouveau_dp_probe_dpcd()
158 u32 link_bw = outp->dp.rate[i].rate; in nouveau_dp_probe_dpcd() local
160 if (link_bw > outp->dp.link_bw) in nouveau_dp_probe_dpcd()
161 outp->dp.link_bw = link_bw; in nouveau_dp_probe_dpcd()
269 nv_encoder->dcb->dpconf.link_bw); in nouveau_dp_detect()
271 nv_encoder->dp.link_bw); in nouveau_dp_detect()
545 max_rate = outp->dp.link_nr * outp->dp.link_bw; in nv50_dp_mode_valid()
A Dnouveau_encoder.h91 int link_bw; member
A Dnouveau_bios.c1475 entry->dpconf.link_bw = 162000; in parse_dcb20_entry()
1478 entry->dpconf.link_bw = 270000; in parse_dcb20_entry()
1481 entry->dpconf.link_bw = 540000; in parse_dcb20_entry()
1485 entry->dpconf.link_bw = 810000; in parse_dcb20_entry()
/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
A Ddcb.c147 outp->dpconf.link_bw = 0x06; in dcb_outp_parse()
150 outp->dpconf.link_bw = 0x0a; in dcb_outp_parse()
153 outp->dpconf.link_bw = 0x14; in dcb_outp_parse()
157 outp->dpconf.link_bw = 0x1e; in dcb_outp_parse()
/drivers/gpu/drm/nouveau/nvif/
A Doutp.c114 u8 link_nr, u32 link_bw, bool mst, bool post_lt_adj, bool retrain) in nvif_outp_dp_train() argument
125 args.link_bw = link_bw; in nvif_outp_dp_train()
132 args.link_bw); in nvif_outp_dp_train()
542 outp->info.dp.link_bw = args.dp.link_bw; in nvif_outp_ctor()
/drivers/gpu/drm/nouveau/include/nvif/
A Doutp.h47 u32 link_bw; member
108 u8 lttprs, u8 link_nr, u32 link_bw, bool mst, bool post_lt_adj,
A Dif0012.h38 __u32 link_bw; member
242 __u32 link_bw; member
/drivers/gpu/drm/i915/display/
A Dintel_dp_link_training.c734 int link_bw, int rate_select, int lane_count, in intel_dp_link_training_set_bw() argument
740 if (link_bw) { in intel_dp_link_training_set_bw()
742 u8 link_config[] = { link_bw, lane_count }; in intel_dp_link_training_set_bw()
763 u8 link_bw, u8 rate_select) in intel_dp_update_link_bw_set() argument
765 intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, crtc_state->lane_count, in intel_dp_update_link_bw_set()
777 u8 link_bw, rate_select; in intel_dp_prepare_link_train() local
783 &link_bw, &rate_select); in intel_dp_prepare_link_train()
796 if (!link_bw) { in intel_dp_prepare_link_train()
805 if (link_bw) in intel_dp_prepare_link_train()
807 link_bw); in intel_dp_prepare_link_train()
[all …]
A Dintel_dp_link_training.h23 int link_bw, int rate_select, int lane_count,
A Dintel_fdi.c328 int lane, link_bw, fdi_dotclock; in ilk_fdi_compute_config() local
337 link_bw = intel_fdi_link_freq(display, pipe_config); in ilk_fdi_compute_config()
341 lane = ilk_get_lanes_required(fdi_dotclock, link_bw, in ilk_fdi_compute_config()
348 link_bw, in ilk_fdi_compute_config()
A Dintel_dp.h113 u8 *link_bw, u8 *rate_select);
A Dintel_dp_mst.c2082 u8 link_bw; in intel_dp_mst_prepare_probe() local
2090 intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select); in intel_dp_mst_prepare_probe()
2093 intel_dp_link_training_set_bw(intel_dp, link_bw, rate_select, lane_count, in intel_dp_mst_prepare_probe()
A Dintel_display.h460 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
/drivers/gpu/drm/nouveau/nvkm/subdev/i2c/
A Danx9805.c193 int link_nr, int link_bw, bool enh) in anx9805_aux_lnk_ctl() argument
201 link_nr, link_bw, enh); in anx9805_aux_lnk_ctl()
203 nvkm_wri2cr(adap, aux->addr, 0xa0, link_bw); in anx9805_aux_lnk_ctl()
A Dauxch.h17 int (*lnk_ctl)(struct nvkm_i2c_aux *, int link_nr, int link_bw,
/drivers/gpu/drm/gma500/
A Dcdv_intel_dp.c261 uint8_t link_bw; member
356 cdv_intel_dp_link_clock(uint8_t link_bw) in cdv_intel_dp_link_clock() argument
358 if (link_bw == DP_LINK_BW_2_7) in cdv_intel_dp_link_clock()
914 intel_dp->link_bw = bws[clock]; in cdv_intel_dp_mode_fixup()
916 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); in cdv_intel_dp_mode_fixup()
919 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
928 intel_dp->link_bw = bws[max_clock]; in cdv_intel_dp_mode_fixup()
929 adjusted_mode->clock = cdv_intel_dp_link_clock(intel_dp->link_bw); in cdv_intel_dp_mode_fixup()
932 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
1068 intel_dp->link_configuration[0] = intel_dp->link_bw; in cdv_intel_dp_mode_set()
/drivers/gpu/drm/amd/display/dc/link/protocols/
A Dlink_dp_capability.c726 uint32_t link_bw; in decide_dp_link_settings() local
737 link_bw = dp_link_bandwidth_kbps( in decide_dp_link_settings()
740 if (req_bw <= link_bw) { in decide_dp_link_settings()
767 uint32_t link_bw; in edp_decide_link_settings() local
792 link_bw = dp_link_bandwidth_kbps( in edp_decide_link_settings()
795 if (req_bw <= link_bw) { in edp_decide_link_settings()
819 uint32_t link_bw; in decide_edp_link_settings_with_dsc() local
848 link_bw = dp_link_bandwidth_kbps( in decide_edp_link_settings_with_dsc()
851 if (req_bw <= link_bw) { in decide_edp_link_settings_with_dsc()
901 link_bw = dp_link_bandwidth_kbps( in decide_edp_link_settings_with_dsc()
[all …]
A Dlink_dp_training.c1771 uint32_t link_bw; in perform_link_training_with_retries() local
1786 link_bw = dp_link_bandwidth_kbps(link, &cur_link_settings); in perform_link_training_with_retries()
1787 is_link_bw_low = (req_bw > link_bw); in perform_link_training_with_retries()
1794 __func__, link->link_index, req_bw, link_bw); in perform_link_training_with_retries()
/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
A Ddcb.h49 int link_bw; member
/drivers/gpu/drm/nouveau/nvkm/engine/disp/
A Duoutp.c121 outp->dp.lt.bw = args->v0.link_bw / 27000; in nvkm_uoutp_mthd_dp_train()
642 args->v0.dp.link_bw = outp->info.dpconf.link_bw * 27000; in nvkm_uoutp_new()
/drivers/gpu/drm/nouveau/include/nvkm/subdev/
A Di2c.h57 int nvkm_i2c_aux_lnk_ctl(struct nvkm_i2c_aux *, int link_nr, int link_bw,
/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/
A Drm.h94 int (*get_caps)(struct nvkm_disp *, int *link_bw, bool *mst, bool *wm);
/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/
A Ddisp.c965 r535_dp_train_target(struct nvkm_outp *outp, u8 target, bool mst, u8 link_nr, u8 link_bw) in r535_dp_train_target() argument
976 NVVAL(NV0073_CTRL, DP_DATA, SET_LINK_BW, link_bw) | in r535_dp_train_target()
1344 ret = rmapi->disp->dp.get_caps(disp, &dcbE.dpconf.link_bw, &mst, &wm); in r535_outp_new()
1348 if (WARN_ON(!dcbE.dpconf.link_bw)) in r535_outp_new()
/drivers/gpu/drm/nouveau/dispnv50/
A Ddisp.c387 max_rate = nv_encoder->dp.link_nr * nv_encoder->dp.link_bw; in nv50_outp_atomic_fix_depth()
1003 mst_state->pbn_div = drm_dp_get_vc_payload_bw(outp->dp.link_bw, outp->dp.link_nr); in nv50_msto_atomic_check()
1612 u64 minRate = outp->dp.link_bw * 1000; in nv50_sor_dp_watermark_sst()
2942 outp->dcb->dpconf.link_bw = outp->outp.info.dp.link_bw; in nv50_display_create()
/drivers/gpu/drm/display/
A Ddrm_dp_helper.c537 int drm_dp_bw_code_to_link_rate(u8 link_bw) in drm_dp_bw_code_to_link_rate() argument
539 switch (link_bw) { in drm_dp_bw_code_to_link_rate()
548 return link_bw * 27000; in drm_dp_bw_code_to_link_rate()

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