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Searched refs:link_rate (Results 1 – 25 of 112) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/link/protocols/
A Dlink_dp_capability.c235 return link_rate; in linkRateInKHzToLinkRateMultiplier()
424 return link_rate; in get_link_rate_from_max_link_bw()
603 dp_lt_fallbacks[cur_idx].link_rate == cur->link_rate) in decide_fallback_link_setting_max_bw_policy()
613 dp_lt_fallbacks[next_idx].link_rate > max->link_rate) in decide_fallback_link_setting_max_bw_policy()
631 cur->link_rate = dp_lt_fallbacks[next_idx].link_rate; in decide_fallback_link_setting_max_bw_policy()
664 cur->link_rate = reduce_link_rate(link, cur->link_rate); in decide_fallback_link_setting()
666 cur->link_rate = max->link_rate; in decide_fallback_link_setting()
686 cur->link_rate = reduce_link_rate(link, cur->link_rate); in decide_fallback_link_setting()
692 max->link_rate = cur->link_rate; in decide_fallback_link_setting()
702 cur->link_rate = reduce_link_rate(link, cur->link_rate); in decide_fallback_link_setting()
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A Dlink_dp_training.c69 link_rate = "RBR"; in dp_log_training_result()
72 link_rate = "R2"; in dp_log_training_result()
75 link_rate = "R3"; in dp_log_training_result()
78 link_rate = "HBR"; in dp_log_training_result()
84 link_rate = "R6"; in dp_log_training_result()
90 link_rate = "R8"; in dp_log_training_result()
171 link_rate, in dp_log_training_result()
399 link_rate = 0; in get_dpcd_link_rate()
403 link_rate = (uint8_t) link_settings->link_rate; in get_dpcd_link_rate()
405 link_rate = 0; in get_dpcd_link_rate()
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/drivers/gpu/drm/tests/
A Ddrm_dp_mst_helper_test.c72 int link_rate; member
93 .link_rate = 2000000,
138 .link_rate = 810000,
143 .link_rate = 810000,
148 .link_rate = 810000,
153 .link_rate = 540000,
158 .link_rate = 540000,
163 .link_rate = 540000,
168 .link_rate = 270000,
173 .link_rate = 270000,
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/drivers/gpu/drm/hisilicon/hibmc/dp/
A Ddp_link.c14 switch (dp->link.cap.link_rate) { in hibmc_dp_get_serdes_rate_cfg()
43 buf[0] = dp->link.cap.link_rate; in hibmc_dp_link_training_configure()
160 switch (dp->link.cap.link_rate) { in hibmc_dp_link_reduce_rate()
162 dp->link.cap.link_rate = DP_LINK_BW_1_62; in hibmc_dp_link_reduce_rate()
165 dp->link.cap.link_rate = DP_LINK_BW_2_7; in hibmc_dp_link_reduce_rate()
168 dp->link.cap.link_rate = DP_LINK_BW_5_4; in hibmc_dp_link_reduce_rate()
337 dp->link.cap.link_rate = dp->dpcd[DP_MAX_LINK_RATE]; in hibmc_dp_link_training()
A Ddp_hw.c27 rate_ks = dp->link.cap.link_rate * HIBMC_DP_LINK_RATE_CAL; in hibmc_dp_set_tu()
55 fclk = dp->link.cap.link_rate * HIBMC_DP_LINK_RATE_CAL; in hibmc_dp_set_sst()
177 dp_dev->link.cap.link_rate = DP_LINK_BW_8_1; in hibmc_dp_hw_init()
/drivers/gpu/drm/i915/display/
A Dintel_dp.h53 int link_rate, int lane_count);
107 int intel_dp_link_config_index(struct intel_dp *intel_dp, int link_rate, int lane_count);
108 void intel_dp_link_config_get(struct intel_dp *intel_dp, int idx, int *link_rate, int *lane_count);
205 bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate,
A Dintel_dp_link_training.c708 link_config[1] = drm_dp_is_uhbr_rate(link_rate) ? in intel_dp_link_training_set_mode()
1177 int link_rate, in intel_dp_can_link_train_fallback_for_edp() argument
1197 int link_rate; in reduce_link_params_in_bw_order() local
1206 intel_dp->link.force_rate != link_rate) || in reduce_link_params_in_bw_order()
1217 *new_link_rate = link_rate; in reduce_link_params_in_bw_order()
1262 int link_rate; in reduce_link_params_in_rate_lane_order() local
1266 link_rate = reduce_link_rate(intel_dp, crtc_state->port_clock); in reduce_link_params_in_rate_lane_order()
1267 if (link_rate < 0) { in reduce_link_params_in_rate_lane_order()
1269 link_rate = intel_dp_max_common_rate(intel_dp); in reduce_link_params_in_rate_lane_order()
1275 *new_link_rate = link_rate; in reduce_link_params_in_rate_lane_order()
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A Dintel_dp_mst.c1161 int link_rate, int lane_count) in intel_mst_probed_link_params_valid() argument
1163 return intel_dp->link.mst_probed_rate == link_rate && in intel_mst_probed_link_params_valid()
1168 int link_rate, int lane_count) in intel_mst_set_probed_link_params() argument
1170 intel_dp->link.mst_probed_rate = link_rate; in intel_mst_set_probed_link_params()
2079 int link_rate = intel_dp_max_link_rate(intel_dp); in intel_dp_mst_prepare_probe() local
2087 if (intel_mst_probed_link_params_valid(intel_dp, link_rate, lane_count)) in intel_dp_mst_prepare_probe()
2090 intel_dp_compute_rate(intel_dp, link_rate, &link_bw, &rate_select); in intel_dp_mst_prepare_probe()
2092 intel_dp_link_training_set_mode(intel_dp, link_rate, false); in intel_dp_mst_prepare_probe()
2096 intel_mst_set_probed_link_params(intel_dp, link_rate, lane_count); in intel_dp_mst_prepare_probe()
A Dintel_dp.c763 link_rate); in intel_dp_link_config_index()
808 if (link_rate == 0 || in intel_dp_link_params_valid()
1776 int mode_rate, link_rate, link_avail; in intel_dp_compute_link_config_wide() local
1787 if (link_rate < limits->min_rate || in intel_dp_compute_link_config_wide()
1788 link_rate > limits->max_rate) in intel_dp_compute_link_config_wide()
1795 link_rate, in intel_dp_compute_link_config_wide()
1977 int link_rate, lane_count; in dsc_compute_link_config() local
1982 if (link_rate < limits->min_rate || link_rate > limits->max_rate) in dsc_compute_link_config()
1998 pipe_config->port_clock = link_rate; in dsc_compute_link_config()
3310 int link_rate, int lane_count) in intel_dp_set_link_params() argument
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A Dintel_dp_link_training.h21 int link_rate, bool is_vrr);
/drivers/phy/qualcomm/
A Dphy-qcom-edp.c291 if (dp_opts->link_rate <= 2700) { in qcom_edp_set_voltages()
344 switch (dp_opts->link_rate) { in qcom_edp_set_vco_div()
413 switch (dp_opts->link_rate) { in qcom_edp_com_configure_ssc_v4()
451 switch (dp_opts->link_rate) { in qcom_edp_com_configure_pll_v4()
598 switch (dp_opts->link_rate) { in qcom_edp_com_configure_ssc_v6()
638 switch (dp_opts->link_rate) { in qcom_edp_com_configure_pll_v6()
857 clk_set_rate(edp->dp_link_hw.clk, edp->dp_opts.link_rate * 100000); in qcom_edp_phy_power_on()
973 switch (dp_opts->link_rate) { in qcom_edp_dp_pixel_clk_recalc_rate()
1013 switch (dp_opts->link_rate) { in qcom_edp_dp_link_clk_recalc_rate()
1018 return dp_opts->link_rate * 100000; in qcom_edp_dp_link_clk_recalc_rate()
/drivers/gpu/drm/bridge/analogix/
A Danalogix_dp_core.c241 analogix_dp_set_link_bandwidth(dp, dp->link_train.link_rate); in analogix_dp_link_start()
255 buf[0] = dp->link_train.link_rate; in analogix_dp_link_start()
492 dp->link_train.link_rate = reg; in analogix_dp_process_equalizer_training()
494 dp->link_train.link_rate); in analogix_dp_process_equalizer_training()
563 if ((dp->link_train.link_rate != DP_LINK_BW_1_62) && in analogix_dp_full_link_train()
564 (dp->link_train.link_rate != DP_LINK_BW_2_7) && in analogix_dp_full_link_train()
565 (dp->link_train.link_rate != DP_LINK_BW_5_4)) { in analogix_dp_full_link_train()
567 dp->link_train.link_rate); in analogix_dp_full_link_train()
568 dp->link_train.link_rate = DP_LINK_BW_1_62; in analogix_dp_full_link_train()
580 if (dp->link_train.link_rate > max_rate) in analogix_dp_full_link_train()
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/drivers/gpu/drm/mediatek/
A Dmtk_dp.c73 int link_rate; member
1257 u32 link_rate, int lane_count) in mtk_dp_phy_configure() argument
1262 .link_rate = drm_dp_bw_code_to_link_rate(link_rate) / 100, in mtk_dp_phy_configure()
1820 link_rate = min_t(u8, mtk_dp->max_linkrate, in mtk_dp_training()
1822 max_link_rate = link_rate; in mtk_dp_training()
1845 switch (link_rate) { in mtk_dp_training()
1848 link_rate = max_link_rate; in mtk_dp_training()
1853 link_rate = DP_LINK_BW_1_62; in mtk_dp_training()
1856 link_rate = DP_LINK_BW_2_7; in mtk_dp_training()
1859 link_rate = DP_LINK_BW_5_4; in mtk_dp_training()
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/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_link_encoder.c995 cntl.pixel_clock = link_settings->link_rate in dcn10_link_encoder_enable_dp_output()
1034 cntl.pixel_clock = link_settings->link_rate in dcn10_link_encoder_enable_dp_mst_output()
1119 cntl.pixel_clock = link_settings->link_rate * LINK_RATE_REF_FREQ_IN_KHZ; in dcn10_link_encoder_dp_set_lane_settings()
1130 if (link_settings->link_rate == LINK_RATE_HIGH2) { in dcn10_link_encoder_dp_set_lane_settings()
1459 max_link_cap.link_rate = LINK_RATE_HIGH2; in dcn10_link_encoder_get_max_link_cap()
1462 max_link_cap.link_rate = LINK_RATE_HIGH3; in dcn10_link_encoder_get_max_link_cap()
1465 max_link_cap.link_rate = LINK_RATE_UHBR10; in dcn10_link_encoder_get_max_link_cap()
1468 max_link_cap.link_rate = LINK_RATE_UHBR13_5; in dcn10_link_encoder_get_max_link_cap()
1471 max_link_cap.link_rate = LINK_RATE_UHBR20; in dcn10_link_encoder_get_max_link_cap()
/drivers/gpu/drm/amd/display/dc/link/
A Dlink_resource.c95 link->verified_link_cap.link_rate = LINK_RATE_HIGH3; in link_restore_res_map()
109 link->verified_link_cap.link_rate = LINK_RATE_HIGH3; in link_restore_res_map()
A Dlink_detection.c563 link->cur_link_settings.link_rate = in read_current_link_settings_on_detect()
573 link->cur_link_settings.link_rate = link_bw_set; in read_current_link_settings_on_detect()
1009 link->reported_link_cap.link_rate > LINK_RATE_HIGH3) in detect_link_and_local_sink()
1010 link->reported_link_cap.link_rate = LINK_RATE_HIGH3; in detect_link_and_local_sink()
1198 if (link->reported_link_cap.link_rate == LINK_RATE_UNKNOWN) in detect_link_and_local_sink()
1200 link->reported_link_cap.link_rate = get_max_edp_link_rate(link); in detect_link_and_local_sink()
/drivers/scsi/mpi3mr/
A Dmpi3mr_transport.c551 switch (link_rate) { in mpi3mr_convert_phy_link_rate()
1107 mpi3mr_convert_phy_link_rate(link_rate); in mpi3mr_update_links()
1133 u8 link_rate; in mpi3mr_sas_host_refresh() local
1159 link_rate = in mpi3mr_sas_host_refresh()
1173 link_rate = MPI3_SAS_NEG_LINK_RATE_1_5; in mpi3mr_sas_host_refresh()
1177 attached_handle, i, link_rate, in mpi3mr_sas_host_refresh()
1998 u8 port_id, link_rate; in mpi3mr_expander_add() local
2083 handle, i, link_rate, hba_port); in mpi3mr_expander_add()
2334 link_rate = (phy_pg0.negotiated_link_rate & in mpi3mr_get_sas_negotiated_logical_linkrate()
2338 return link_rate; in mpi3mr_get_sas_negotiated_logical_linkrate()
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/drivers/phy/mediatek/
A Dphy-mtk-dp.c115 switch (opts->dp.link_rate) { in mtk_dp_phy_configure()
119 opts->dp.link_rate); in mtk_dp_phy_configure()
/drivers/gpu/drm/rockchip/
A Dcdn-dp-reg.c635 u32 val, link_rate, rem; in cdn_dp_config_video() local
642 link_rate = dp->max_rate / 1000; in cdn_dp_config_video()
662 do_div(symbol, dp->max_lanes * link_rate * 8); in cdn_dp_config_video()
668 mode->clock, dp->max_lanes, link_rate); in cdn_dp_config_video()
681 val = div_u64(mode->clock * (symbol + 1), 1000) + link_rate; in cdn_dp_config_video()
682 val /= (dp->max_lanes * link_rate); in cdn_dp_config_video()
/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_link_encoder.c1140 cntl.pixel_clock = link_settings->link_rate in dce110_link_encoder_enable_dp_output()
1179 cntl.pixel_clock = link_settings->link_rate in dce110_link_encoder_enable_dp_mst_output()
1219 cntl.pixel_clock = link_settings->link_rate in dce60_link_encoder_enable_dp_output()
1258 cntl.pixel_clock = link_settings->link_rate in dce60_link_encoder_enable_dp_mst_output()
1340 cntl.pixel_clock = link_settings->link_rate * in dce110_link_encoder_dp_set_lane_settings()
1352 if (link_settings->link_rate == LINK_RATE_HIGH2) { in dce110_link_encoder_dp_set_lane_settings()
1674 max_link_cap.link_rate = LINK_RATE_HIGH2; in dce110_link_encoder_get_max_link_cap()
1677 max_link_cap.link_rate = LINK_RATE_HIGH3; in dce110_link_encoder_get_max_link_cap()
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_debugfs.c211 link->cur_link_settings.link_rate, in dp_link_settings_read()
218 link->verified_link_cap.link_rate, in dp_link_settings_read()
225 link->reported_link_cap.link_rate, in dp_link_settings_read()
232 link->preferred_link_setting.link_rate, in dp_link_settings_read()
332 prefer_link_settings.link_rate = param[1]; in dp_link_settings_write()
466 prefer_link_settings.link_rate = param[1]; in dp_mst_link_setting()
663 link->preferred_link_setting.link_rate; in dp_phy_settings_write()
670 link->cur_link_settings.link_rate; in dp_phy_settings_write()
856 prefer_link_settings.link_rate = link->verified_link_cap.link_rate; in dp_phy_test_pattern_debugfs_write()
860 cur_link_settings.link_rate = link->cur_link_settings.link_rate; in dp_phy_test_pattern_debugfs_write()
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/drivers/scsi/pm8001/
A Dpm8001_init.c51 static ulong link_rate = LINKRATE_15 | LINKRATE_30 | LINKRATE_60 | LINKRATE_120; variable
52 module_param(link_rate, ulong, 0644);
53 MODULE_PARM_DESC(link_rate, "Enable link rate.\n"
555 if (link_rate >= 1 && link_rate <= 15) in pm8001_pci_alloc()
556 pm8001_ha->link_rate = (link_rate << 8); in pm8001_pci_alloc()
558 pm8001_ha->link_rate = LINKRATE_15 | LINKRATE_30 | in pm8001_pci_alloc()
/drivers/gpu/drm/bridge/cadence/
A Dcdns-mhdp8546-core.c577 return min(mhdp->host.link_rate, mhdp->sink.link_rate); in cdns_mhdp_max_link_rate()
829 phy_cfg.dp.link_rate = mhdp->link.rate / 100; in cdns_mhdp_link_training_init()
1302 unsigned int link_rate; in cdns_mhdp_fill_host_caps() local
1310 link_rate = mhdp->phy->attrs.max_link_rate; in cdns_mhdp_fill_host_caps()
1311 if (!link_rate) in cdns_mhdp_fill_host_caps()
1312 link_rate = drm_dp_bw_code_to_link_rate(DP_LINK_BW_8_1); in cdns_mhdp_fill_host_caps()
1315 link_rate *= 100; in cdns_mhdp_fill_host_caps()
1317 mhdp->host.link_rate = link_rate; in cdns_mhdp_fill_host_caps()
1333 mhdp->sink.link_rate = mhdp->link.rate; in cdns_mhdp_fill_sink_caps()
2222 mhdp->link.rate = mhdp->host.link_rate; in cdns_mhdp_update_link_status()
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/drivers/gpu/drm/amd/display/dc/link/accessories/
A Dlink_dp_cts.c164 link_settings.link_rate = get_link_rate_from_test_link_rate(test_rate); in dp_test_send_link_training()
166 if (link_settings.link_rate == LINK_RATE_UNKNOWN) { in dp_test_send_link_training()
173 link->verified_link_cap.link_rate = link_settings.link_rate; in dp_test_send_link_training()
999 link->preferred_link_setting.link_rate = LINK_RATE_UNKNOWN; in dp_set_preferred_training_settings()
/drivers/phy/rockchip/
A Dphy-rockchip-usbdp.c190 unsigned int link_rate; member
1113 switch (dp->link_rate) { in rk_udphy_dp_phy_verify_link_rate()
1118 udphy->link_rate = dp->link_rate; in rk_udphy_dp_phy_verify_link_rate()
1226 switch (dp->link_rate) { in rk_udphy_dp_phy_configure()
1267 switch (udphy->link_rate) { in rk_udphy_dp_phy_configure()

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