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Searched refs:link_settings (Results 1 – 25 of 80) sorted by relevance

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/drivers/gpu/drm/amd/display/dc/link/protocols/
A Dlink_dp_phy.c63 const struct dc_link_settings *link_settings) in dp_enable_link_phy() argument
65 link->cur_link_settings = *link_settings; in dp_enable_link_phy()
67 clock_source, link_settings); in dp_enable_link_phy()
100 const struct link_training_settings *link_settings, in dp_set_hw_lane_settings() argument
106 if ((link_settings->lttpr_mode == LTTPR_MODE_NON_TRANSPARENT) && in dp_set_hw_lane_settings()
109 link_dp_get_encoding_format(&link_settings->link_settings) == DP_8b_10b_ENCODING)) in dp_set_hw_lane_settings()
114 &link_settings->link_settings, in dp_set_hw_lane_settings()
115 link_settings->hw_lane_settings); in dp_set_hw_lane_settings()
118 link_settings->hw_lane_settings, in dp_set_hw_lane_settings()
A Dlink_dp_training_8b_10b.c50 const struct dc_link_settings *link_settings, in get_cr_training_aux_rd_interval() argument
57 if (link_dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) { in get_cr_training_aux_rd_interval()
79 const struct dc_link_settings *link_settings) in get_eq_training_aux_rd_interval() argument
84 if (link_dp_get_encoding_format(link_settings) == DP_128b_132b_ENCODING) { in get_eq_training_aux_rd_interval()
123 lt_settings->link_settings.link_rate_set = link_setting->link_rate_set; in decide_8b_10b_training_settings()
124 lt_settings->link_settings.link_rate = link_setting->link_rate; in decide_8b_10b_training_settings()
125 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
133 lt_settings->link_settings.link_spread = link->dp_ss_off ? in decide_8b_10b_training_settings()
230 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_clock_recovery_sequence()
304 if ((link_dp_get_encoding_format(&lt_settings->link_settings) == in perform_8b_10b_clock_recovery_sequence()
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A Dlink_dp_training.c172 lt_settings->link_settings.lane_count, in dp_log_training_result()
388 switch (link_settings->link_rate) { in get_dpcd_link_rate()
1047 &lt_settings->link_settings); in dpcd_configure_channel_coding()
1099 (lt_settings->link_settings.link_spread); in dpcd_set_link_settings()
1102 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
1157 lt_settings->link_settings.link_rate, in dpcd_set_link_settings()
1159 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1162 lt_settings->link_settings.link_spread); in dpcd_set_link_settings()
1169 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1421 lt_settings->link_settings.lane_count; in perform_post_lt_adj_req_sequence()
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A Dlink_dp_training_128b_132b.c118 } else if (dp_is_ch_eq_done(lt_settings->link_settings.lane_count, in dp_perform_128b_132b_channel_eq_done_sequence()
181 } else if (dp_is_symbol_locked(lt_settings->link_settings.lane_count, dpcd_lane_status) && in dp_perform_128b_132b_cds_done_sequence()
208 &lt_settings->link_settings, in dp_perform_128b_132b_link_training()
232 const struct dc_link_settings *link_settings, in decide_128b_132b_training_settings() argument
237 lt_settings->link_settings = *link_settings; in decide_128b_132b_training_settings()
239 lt_settings->link_settings.link_spread = link->dp_ss_off ? LINK_SPREAD_DISABLED : in decide_128b_132b_training_settings()
242 lt_settings->pattern_for_cr = decide_cr_training_pattern(link_settings); in decide_128b_132b_training_settings()
243 lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_settings); in decide_128b_132b_training_settings()
A Dlink_dp_training_fixed_vs_pe_retimer.c119 target_rate = get_dpcd_link_rate(&lt_settings->link_settings); in perform_fixed_vs_pe_nontransparent_training_sequence()
123 lt_settings->link_settings.link_rate = toggle_rate; in perform_fixed_vs_pe_nontransparent_training_sequence()
219 ASSERT(link_dp_get_encoding_format(&lt_settings->link_settings) == in dp_perform_fixed_vs_pe_training_sequence()
251 downspread.raw = (uint8_t)(lt_settings->link_settings.link_spread); in dp_perform_fixed_vs_pe_training_sequence()
254 lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence()
271 rate = get_dpcd_link_rate(&lt_settings->link_settings); in dp_perform_fixed_vs_pe_training_sequence()
294 lt_settings->link_settings.link_rate, in dp_perform_fixed_vs_pe_training_sequence()
296 lt_settings->link_settings.lane_count, in dp_perform_fixed_vs_pe_training_sequence()
299 lt_settings->link_settings.link_spread); in dp_perform_fixed_vs_pe_training_sequence()
305 if (lt_settings->link_settings.lane_count == LANE_COUNT_FOUR) { in dp_perform_fixed_vs_pe_training_sequence()
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A Dlink_dp_training.h42 const struct dc_link_settings *link_settings,
108 const struct dc_link_settings *link_settings,
118 const struct dc_link_settings *link_settings);
122 const struct dc_link_settings *link_settings);
154 uint8_t get_dpcd_link_rate(const struct dc_link_settings *link_settings);
A Dlink_dp_phy.h35 const struct dc_link_settings *link_settings);
44 const struct link_training_settings *link_settings,
/drivers/gpu/drm/amd/display/dc/dio/dcn31/
A Ddcn31_dio_link_encoder.c452 const struct dc_link_settings *link_settings, in dcn31_link_encoder_enable_dp_output() argument
470 enc1_configure_encoder(enc10, link_settings); in dcn31_link_encoder_enable_dp_output()
475 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_output()
476 dpia_control.symclk_10khz = link_settings->link_rate * in dcn31_link_encoder_enable_dp_output()
499 const struct dc_link_settings *link_settings, in dcn31_link_encoder_enable_dp_mst_output() argument
517 enc1_configure_encoder(enc10, link_settings); in dcn31_link_encoder_enable_dp_mst_output()
522 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_mst_output()
523 dpia_control.symclk_10khz = link_settings->link_rate * in dcn31_link_encoder_enable_dp_mst_output()
642 dcn10_link_encoder_get_max_link_cap(enc, link_settings); in dcn31_link_encoder_get_max_link_cap()
659 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
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/drivers/gpu/drm/amd/display/dc/dio/dcn20/
A Ddcn20_link_encoder.c213 const struct dc_link_settings *link_settings, in update_cfg_data() argument
220 for (i = 0; i < link_settings->lane_count; i++) in update_cfg_data()
223 switch (link_settings->link_rate) { in update_cfg_data()
238 __func__, link_settings->link_rate); in update_cfg_data()
247 const struct dc_link_settings *link_settings, in dcn20_link_encoder_enable_dp_output() argument
255 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); in dcn20_link_encoder_enable_dp_output()
259 if (!update_cfg_data(enc10, link_settings, cfg)) in dcn20_link_encoder_enable_dp_output()
262 enc1_configure_encoder(enc10, link_settings); in dcn20_link_encoder_enable_dp_output()
269 struct dc_link_settings *link_settings) in dcn20_link_encoder_get_max_link_cap() argument
274 dcn10_link_encoder_get_max_link_cap(enc, link_settings); in dcn20_link_encoder_get_max_link_cap()
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/drivers/gpu/drm/amd/display/dc/dce/
A Ddce_link_encoder.c599 const struct dc_link_settings *link_settings) in configure_encoder() argument
613 const struct dc_link_settings *link_settings) in dce60_configure_encoder() argument
1131 configure_encoder(enc110, link_settings); in dce110_link_encoder_enable_dp_output()
1140 cntl.pixel_clock = link_settings->link_rate in dce110_link_encoder_enable_dp_output()
1170 configure_encoder(enc110, link_settings); in dce110_link_encoder_enable_dp_mst_output()
1179 cntl.pixel_clock = link_settings->link_rate in dce110_link_encoder_enable_dp_mst_output()
1219 cntl.pixel_clock = link_settings->link_rate in dce60_link_encoder_enable_dp_output()
1258 cntl.pixel_clock = link_settings->link_rate in dce60_link_encoder_enable_dp_mst_output()
1330 if (!link_settings) { in dce110_link_encoder_dp_set_lane_settings()
1666 struct dc_link_settings *link_settings) in dce110_link_encoder_get_max_link_cap() argument
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/drivers/gpu/drm/amd/display/dc/dio/dcn35/
A Ddcn35_dio_link_encoder.c302 const struct dc_link_settings *link_settings, in dcn35_link_encoder_enable_dp_output() argument
308 dcn31_link_encoder_enable_dp_output(enc, link_settings, clock_source); in dcn35_link_encoder_enable_dp_output()
311 dcn20_link_encoder_enable_dp_output(enc, link_settings, clock_source); in dcn35_link_encoder_enable_dp_output()
317 const struct dc_link_settings *link_settings, in dcn35_link_encoder_enable_dp_mst_output() argument
323 dcn31_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source); in dcn35_link_encoder_enable_dp_mst_output()
326 dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source); in dcn35_link_encoder_enable_dp_mst_output()
346 const struct dc_link_settings *link_settings, in dcn35_link_encoder_enable_dpia_output() argument
354 enc1_configure_encoder(enc10, link_settings); in dcn35_link_encoder_enable_dpia_output()
359 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn35_link_encoder_enable_dpia_output()
360 dpia_control.symclk_10khz = link_settings->link_rate * in dcn35_link_encoder_enable_dpia_output()
/drivers/gpu/drm/amd/display/dc/virtual/
A Dvirtual_link_encoder.c50 const struct dc_link_settings *link_settings, in virtual_link_encoder_enable_dp_output() argument
55 const struct dc_link_settings *link_settings, in virtual_link_encoder_enable_dp_mst_output() argument
64 const struct dc_link_settings *link_settings, in virtual_link_encoder_dp_set_lane_settings() argument
87 struct dc_link_settings *link_settings) in virtual_link_encoder_get_max_link_cap() argument
92 *link_settings = max_link_cap; in virtual_link_encoder_get_max_link_cap()
/drivers/gpu/drm/amd/display/dc/inc/hw/
A Dlink_encoder.h121 const struct dc_link_settings *link_settings,
124 const struct dc_link_settings *link_settings,
132 const struct dc_link_settings *link_settings,
162 struct dc_link_settings *link_settings);
172 const struct dc_link_settings *link_settings,
246 const struct dc_link_settings *link_settings,
282 const struct dc_link_settings *link_settings,
/drivers/gpu/drm/amd/display/dc/dcn21/
A Ddcn21_link_encoder.c171 const struct dc_link_settings *link_settings, in update_cfg_data() argument
183 switch (link_settings->link_rate) { in update_cfg_data()
198 __func__, link_settings->link_rate); in update_cfg_data()
255 const struct dc_link_settings *link_settings, in dcn21_link_encoder_enable_dp_output() argument
266 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); in dcn21_link_encoder_enable_dp_output()
270 if (!update_cfg_data(enc10, link_settings, cfg)) in dcn21_link_encoder_enable_dp_output()
273 enc1_configure_encoder(enc10, link_settings); in dcn21_link_encoder_enable_dp_output()
281 const struct dc_link_settings *link_settings, in dcn21_link_encoder_enable_dp_mst_output() argument
287 dcn10_link_encoder_enable_dp_mst_output(enc, link_settings, clock_source); in dcn21_link_encoder_enable_dp_mst_output()
/drivers/gpu/drm/amd/display/dc/dio/dcn10/
A Ddcn10_link_encoder.c488 const struct dc_link_settings *link_settings) in enc1_configure_encoder() argument
973 const struct dc_link_settings *link_settings, in dcn10_link_encoder_enable_dp_output() argument
986 enc1_configure_encoder(enc10, link_settings); in dcn10_link_encoder_enable_dp_output()
995 cntl.pixel_clock = link_settings->link_rate in dcn10_link_encoder_enable_dp_output()
1012 const struct dc_link_settings *link_settings, in dcn10_link_encoder_enable_dp_mst_output() argument
1025 enc1_configure_encoder(enc10, link_settings); in dcn10_link_encoder_enable_dp_mst_output()
1034 cntl.pixel_clock = link_settings->link_rate in dcn10_link_encoder_enable_dp_mst_output()
1100 const struct dc_link_settings *link_settings, in dcn10_link_encoder_dp_set_lane_settings() argument
1109 if (!link_settings) { in dcn10_link_encoder_dp_set_lane_settings()
1451 struct dc_link_settings *link_settings) in dcn10_link_encoder_get_max_link_cap() argument
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/drivers/gpu/drm/amd/display/dc/link/hwss/
A Dlink_hwss_hpo_dp.c47 const struct dc_link_settings *link_settings, in set_hpo_dp_hblank_min_symbol_width() argument
56 pipe_ctx->stream->link, link_settings); in set_hpo_dp_hblank_min_symbol_width()
111 const struct dc_link_settings *link_settings) in enable_hpo_dp_link_output() argument
125 link_settings, in enable_hpo_dp_link_output()
160 const struct dc_link_settings *link_settings, in set_hpo_dp_lane_settings() argument
165 link_settings, in set_hpo_dp_lane_settings()
A Dlink_hwss_hpo_dp.h34 const struct dc_link_settings *link_settings,
37 const struct dc_link_settings *link_settings,
46 const struct dc_link_settings *link_settings);
A Dlink_hwss_dpia.c81 const struct dc_link_settings *link_settings, in set_dio_dpia_lane_settings() argument
90 const struct dc_link_settings *link_settings) in enable_dpia_link_output() argument
106 link_settings, in enable_dpia_link_output()
113 enable_dio_dp_link_output(link, link_res, signal, clock_source, link_settings); in enable_dpia_link_output()
A Dlink_hwss_hpo_fixed_vs_pe_retimer_dp.c178 const struct dc_link_settings *link_settings, in set_hpo_fixed_vs_pe_retimer_dp_lane_settings() argument
190 link_settings, in set_hpo_fixed_vs_pe_retimer_dp_lane_settings()
199 const struct dc_link_settings *link_settings) in enable_hpo_fixed_vs_pe_retimer_dp_link_output() argument
201 if (link_settings->lane_count == LANE_COUNT_FOUR) in enable_hpo_fixed_vs_pe_retimer_dp_link_output()
204 enable_hpo_dp_link_output(link, link_res, signal, clock_source, link_settings); in enable_hpo_fixed_vs_pe_retimer_dp_link_output()
A Dlink_hwss_dio.c157 const struct dc_link_settings *link_settings) in enable_dio_dp_link_output() argument
171 link_settings, in enable_dio_dp_link_output()
176 link_settings, in enable_dio_dp_link_output()
219 const struct dc_link_settings *link_settings, in set_dio_dp_lane_settings() argument
231 link_enc->funcs->dp_set_lane_settings(link_enc, link_settings, lane_settings); in set_dio_dp_lane_settings()
/drivers/gpu/drm/amd/display/dc/dio/dcn32/
A Ddcn32_dio_link_encoder.c144 const struct dc_link_settings *link_settings, in dcn32_link_encoder_enable_dp_output() argument
148 dcn10_link_encoder_enable_dp_output(enc, link_settings, clock_source); in dcn32_link_encoder_enable_dp_output()
182 struct dc_link_settings *link_settings) in dcn32_link_encoder_get_max_link_cap() argument
186 dcn10_link_encoder_get_max_link_cap(enc, link_settings); in dcn32_link_encoder_get_max_link_cap()
193 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn32_link_encoder_get_max_link_cap()
A Ddcn32_dio_link_encoder.h45 const struct dc_link_settings *link_settings,
51 struct dc_link_settings *link_settings);
/drivers/gpu/drm/amd/display/dc/inc/
A Dlink_hwss.h50 const struct dc_link_settings *link_settings,
58 const struct dc_link_settings *link_settings);
64 const struct dc_link_settings *link_settings,
/drivers/gpu/drm/amd/display/dc/dcn201/
A Ddcn201_link_encoder.c53 struct dc_link_settings *link_settings) in dcn201_link_encoder_get_max_link_cap() argument
58 dcn10_link_encoder_get_max_link_cap(enc, link_settings); in dcn201_link_encoder_get_max_link_cap()
63 if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO) in dcn201_link_encoder_get_max_link_cap()
64 link_settings->lane_count = LANE_COUNT_TWO; in dcn201_link_encoder_get_max_link_cap()
/drivers/net/ethernet/huawei/hinic/
A Dhinic_ethtool.c211 (link_settings, idx); in hinic_add_ethtool_link_mode()
214 (link_settings, idx); in hinic_add_ethtool_link_mode()
225 ETHTOOL_ADD_SUPPORTED_LINK_MODE(link_settings, TP); in hinic_link_port_type()
226 ETHTOOL_ADD_ADVERTISED_LINK_MODE(link_settings, TP); in hinic_link_port_type()
227 link_settings->port = PORT_TP; in hinic_link_port_type()
234 link_settings->port = PORT_FIBRE; in hinic_link_port_type()
240 link_settings->port = PORT_DA; in hinic_link_port_type()
246 link_settings->port = PORT_NONE; in hinic_link_port_type()
250 link_settings->port = PORT_OTHER; in hinic_link_port_type()
522 ethtool_link_ksettings *link_settings) in hinic_set_link_ksettings() argument
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