Home
last modified time | relevance | path

Searched refs:link_train (Results 1 – 3 of 3) sorted by relevance

/drivers/gpu/drm/bridge/analogix/
A Danalogix_dp_core.c235 dp->link_train.eq_loop = 0; in analogix_dp_link_start()
238 dp->link_train.cr_loop[lane] = 0; in analogix_dp_link_start()
360 dp->link_train.lt_state = FAILED; in analogix_dp_reduce_link_rate()
435 dp->link_train.cr_loop[lane], in analogix_dp_process_clock_recovery()
492 dp->link_train.link_rate = reg; in analogix_dp_process_equalizer_training()
494 dp->link_train.link_rate); in analogix_dp_process_equalizer_training()
499 dp->link_train.lane_count); in analogix_dp_process_equalizer_training()
507 dp->link_train.eq_loop++; in analogix_dp_process_equalizer_training()
567 dp->link_train.link_rate); in analogix_dp_full_link_train()
573 dp->link_train.lane_count); in analogix_dp_full_link_train()
[all …]
A Danalogix_dp_core.h142 struct link_train { struct
165 struct link_train link_train; argument
A Danalogix_dp_reg.c527 drm_dp_bw_code_to_link_rate(dp->link_train.link_rate) / 100; in analogix_dp_set_link_bandwidth()
556 phy_cfg.dp.lanes = dp->link_train.lane_count; in analogix_dp_set_lane_count()
579 for (lane = 0; lane < dp->link_train.lane_count; lane++) in analogix_dp_set_lane_link_training()
580 writel(dp->link_train.training_lane[lane], in analogix_dp_set_lane_link_training()
586 for (lane = 0; lane < dp->link_train.lane_count; lane++) { in analogix_dp_set_lane_link_training()
587 u8 training_lane = dp->link_train.training_lane[lane]; in analogix_dp_set_lane_link_training()

Completed in 13 milliseconds