| /drivers/gpu/drm/amd/display/dc/mpc/dcn401/ |
| A D | dcn401_mpc.c | 120 const struct dc_rgb *lut2; in mpc401_populate_lut() local
174 lut2 = lut3d->tetrahedral_17.lut2; in mpc401_populate_lut()
183 lut2 = lut3d->tetrahedral_9.lut2; in mpc401_populate_lut()
207 mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id); in mpc401_populate_lut()
209 mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id); in mpc401_populate_lut()
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| /drivers/gpu/drm/amd/display/dc/inc/hw/ |
| A D | hw_shared.h | 103 struct dc_rgb lut2[1228]; member
109 struct dc_rgb lut2[182]; member
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| A D | dpp.h | 171 int lut2; member
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| /drivers/gpu/drm/amd/display/amdgpu_dm/ |
| A D | amdgpu_dm_color.c | 688 struct dc_rgb *lut2; in __drm_3dlut_to_dc_3dlut() local
696 lut2 = params->tetrahedral_9.lut2; in __drm_3dlut_to_dc_3dlut()
701 lut2 = params->tetrahedral_17.lut2; in __drm_3dlut_to_dc_3dlut()
717 __to_dc_lut3d_color(&lut2[lut_i], lut[i + 2], bit_depth); in __drm_3dlut_to_dc_3dlut()
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| /drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| A D | dcn20_dpp_cm.c | 1124 const struct dc_rgb *lut2; in dpp20_program_3dlut() local
1145 lut2 = params->tetrahedral_17.lut2; in dpp20_program_3dlut()
1154 lut2 = params->tetrahedral_9.lut2; in dpp20_program_3dlut()
1178 dpp20_set3dlut_ram12(dpp_base, lut2, lut_size); in dpp20_program_3dlut()
1180 dpp20_set3dlut_ram10(dpp_base, lut2, lut_size); in dpp20_program_3dlut()
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| A D | dcn20_dpp.c | 223 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp2_cnv_setup()
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| /drivers/gpu/drm/amd/display/dc/mpc/dcn32/ |
| A D | dcn32_mpc.c | 918 const struct dc_rgb *lut2; in mpc32_program_3dlut() local
941 lut2 = params->tetrahedral_17.lut2; in mpc32_program_3dlut()
950 lut2 = params->tetrahedral_9.lut2; in mpc32_program_3dlut()
974 mpc32_set3dlut_ram12(mpc, lut2, lut_size, mpcc_id); in mpc32_program_3dlut()
976 mpc32_set3dlut_ram10(mpc, lut2, lut_size, mpcc_id); in mpc32_program_3dlut()
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| /drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| A D | dcn30_dpp.c | 340 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp3_cnv_setup()
1393 const struct dc_rgb *lut2; in dpp3_program_3dlut() local
1419 lut2 = params->tetrahedral_17.lut2; in dpp3_program_3dlut()
1428 lut2 = params->tetrahedral_9.lut2; in dpp3_program_3dlut()
1452 dpp3_set3dlut_ram12(dpp_base, lut2, lut_size); in dpp3_program_3dlut()
1454 dpp3_set3dlut_ram10(dpp_base, lut2, lut_size); in dpp3_program_3dlut()
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| /drivers/gpu/drm/amd/display/dc/mpc/dcn30/ |
| A D | dcn30_mpc.c | 1228 const struct dc_rgb *lut2; in mpc3_program_3dlut() local
1251 lut2 = params->tetrahedral_17.lut2; in mpc3_program_3dlut()
1260 lut2 = params->tetrahedral_9.lut2; in mpc3_program_3dlut()
1284 mpc3_set3dlut_ram12(mpc, lut2, lut_size, rmu_idx); in mpc3_program_3dlut()
1286 mpc3_set3dlut_ram10(mpc, lut2, lut_size, rmu_idx); in mpc3_program_3dlut()
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| /drivers/gpu/drm/amd/display/modules/color/ |
| A D | color_gamma.c | 1431 struct fixed31_32 lut2; in apply_lut_1d() local
1477 lut2 = ramp->entries.red[index_next]; in apply_lut_1d()
1480 lut2 = ramp->entries.green[index_next]; in apply_lut_1d()
1483 lut2 = ramp->entries.blue[index_next]; in apply_lut_1d()
1487 delta_lut = dc_fixpt_sub(lut2, lut1); in apply_lut_1d()
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| /drivers/gpu/drm/i915/display/ |
| A D | intel_color.c | 3121 const struct drm_color_lut *lut2, u32 err) in err_check() argument
3123 return ((abs((long)lut2->red - lut1->red)) <= err) && in err_check()
3124 ((abs((long)lut2->blue - lut1->blue)) <= err) && in err_check()
3125 ((abs((long)lut2->green - lut1->green)) <= err); in err_check()
3129 const struct drm_color_lut *lut2, in intel_lut_entries_equal() argument
3135 if (!err_check(&lut1[i], &lut2[i], err)) in intel_lut_entries_equal()
3146 const struct drm_color_lut *lut1, *lut2; in intel_lut_equal() local
3169 lut2 = blob2->data; in intel_lut_equal()
3176 return intel_lut_entries_equal(lut1, lut2, check_size, err); in intel_lut_equal()
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| /drivers/gpu/drm/amd/display/dc/dpp/dcn201/ |
| A D | dcn201_dpp.c | 169 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp201_cnv_setup()
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| /drivers/gpu/drm/amd/display/dc/dpp/dcn401/ |
| A D | dcn401_dpp.c | 186 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2); in dpp401_dpp_setup()
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