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Searched refs:m0 (Results 1 – 25 of 29) sorted by relevance

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/drivers/gpu/drm/amd/amdkfd/
A Dcwsr_trap_handler_gfx10.asm494 s_and_b32 m0, m0, 1
668 s_and_b32 m0, m0, 1
705 s_and_b32 m0, m0, 1
790 s_and_b32 m0, m0, 1
805 s_and_b32 m0, m0, 1
830 s_add_u32 m0, m0, 4
875 s_add_u32 m0, m0, 4
919 s_add_u32 m0, m0, 1
955 s_and_b32 m0, m0, 1
980 s_and_b32 m0, m0, 1
[all …]
A Dcwsr_trap_handler_gfx12.asm381 s_and_b32 m0, m0, 1
536 s_and_b32 m0, m0, 1
572 s_and_b32 m0, m0, 1
617 s_and_b32 m0, m0, 1
632 s_and_b32 m0, m0, 1
730 s_and_b32 m0, m0, 1
755 s_and_b32 m0, m0, 1
764 s_add_u32 m0, m0, 128 // 128 DW
774 s_add_u32 m0, m0, 256 // 256 DW
785 s_and_b32 m0, m0, 1
[all …]
A Dcwsr_trap_handler_gfx9.asm497 s_add_u32 m0, m0, 16 //next sgpr index
658 s_add_u32 m0, m0, 4
674 s_add_u32 m0, m0, 4 //next vgpr index
707 s_add_u32 m0, m0, 4
722 s_add_u32 m0, m0, 4
787 s_add_u32 m0, m0, LDS_RESTORE_GRANULARITY_BYTES // 128/320 DW
817 s_add_u32 m0, m0, 4 //next vgpr index
832 s_mov_b32 m0, 0
842 s_add_u32 m0, m0, 4 //next vgpr index
877 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0]
[all …]
A Dcwsr_trap_handler_gfx8.asm330 … s_add_u32 m0, m0, 16 //next sgpr index
399 s_mov_b32 m0, 0x10000
437 s_cmp_lt_u32 m0, s_save_alloc_size
455 … s_add_u32 m0, m0, 4 //next vgpr index
519 s_add_u32 m0, m0, 256*2 // 128 DW
556 …s_add_u32 m0, m0, 4 //next vgp…
588 s_mov_b32 m0, s_restore_alloc_size
594 s_sub_u32 m0, m0, 16 // Restore from S[n] to S[0]
636 s_mov_b32 m0, s_restore_m0
688 s_mov_b32 m0, s_mem_offset
[all …]
/drivers/gpu/drm/amd/amdgpu/
A Dgfx_v9_4_3_cleaner_shader.asm59 s_movk_i32 m0, 0x0000
93 s_mov_b32 m0, 0xffffffff
107 s_mov_b32 m0, 0x0000005c // Loop 96/4=24 times (loop unrolled for performance)
114 s_sub_u32 m0, m0, 4
135 s_mov_b32 m0, 0x0000005c // Loop 96/4=24 times (loop unrolled for performance)
143 s_sub_u32 m0, m0, 4
A Dgfx_v9_4_2_cleaner_shader.asm59 s_movk_i32 m0, 0x0000
93 s_mov_b32 m0, 0xffffffff
107 s_mov_b32 m0, 0x0000005c // Loop 96/4=24 times (loop unrolled for performance)
114 s_sub_u32 m0, m0, 4
135 s_mov_b32 m0, 0x0000005c // Loop 96/4=24 times (loop unrolled for performance)
143 s_sub_u32 m0, m0, 4
A Dgfx_v11_0_3_cleaner_shader.asm52 s_mov_b32 m0, 0x00000058 // Loop 96/8=12 times (loop unrolled for performance)
63 s_sub_u32 m0, m0, 8
79 s_mov_b32 m0, 0xffffffff
93 s_mov_b32 m0, 0x00000068 // Loop 108/4=27 times (loop unrolled for performance)
99 s_sub_u32 m0, m0, 4
A Dgfx_v10_3_0_cleaner_shader.asm55 s_mov_b32 m0, 0
68 s_mov_b32 m0, s2
83 s_mov_b32 m0, 0xffffffff
98 s_mov_b32 m0, 0x00000068 // Loop 108/4=27 times (loop unrolled for performance)
104 s_sub_u32 m0, m0, 4
A Dgfx_v10_1_10_cleaner_shader.asm56 s_mov_b32 m0, 0
69 s_mov_b32 m0, s2
84 s_mov_b32 m0, 0xffffffff
99 s_mov_b32 m0, 0x00000068 // Loop 108/4=27 times (loop unrolled for performance)
105 s_sub_u32 m0, m0, 4
/drivers/net/ethernet/apm/xgene-v2/
A Dmain.c102 raw_desc->m0 = cpu_to_le64(SET_BITS(PKT_ADDRL, dma_addr) | in xge_refill_buffers()
163 if (GET_BITS(E, le64_to_cpu(raw_desc->m0)) && in is_tx_slot_available()
164 (GET_BITS(PKT_SIZE, le64_to_cpu(raw_desc->m0)) == SLOT_EMPTY)) in is_tx_slot_available()
214 raw_desc->m0 = cpu_to_le64(SET_BITS(PKT_ADDRL, dma_addr) | in xge_start_xmit()
227 if (GET_BITS(E, le64_to_cpu(raw_desc->m0)) && in is_tx_hw_done()
228 !GET_BITS(PKT_SIZE, le64_to_cpu(raw_desc->m0))) in is_tx_hw_done()
270 raw_desc->m0 = cpu_to_le64(SET_BITS(E, 1) | in xge_txc_poll()
307 if (GET_BITS(E, le64_to_cpu(raw_desc->m0))) in xge_rx_poll()
315 len = GET_BITS(PKT_SIZE, le64_to_cpu(raw_desc->m0)); in xge_rx_poll()
543 if (!GET_BITS(E, le64_to_cpu(raw_desc->m0))) in is_tx_pending()
A Dring.c26 raw_desc->m0 = cpu_to_le64(SET_BITS(E, 1) | in xge_setup_desc()
A Dring.h56 __le64 m0; member
/drivers/dma/
A Dxgene-dma.c200 __le64 m0; member
391 return &desc->m0; in xgene_dma_lookup_ext8()
406 desc->m0 |= cpu_to_le64(XGENE_DMA_DESC_IN_BIT); in xgene_dma_init_desc()
407 desc->m0 |= cpu_to_le64((u64)XGENE_DMA_RING_OWNER_DMA << in xgene_dma_init_desc()
435 desc1->m0 |= cpu_to_le64(XGENE_DMA_DESC_NV_BIT); in xgene_dma_prep_xor_desc()
708 if (unlikely(le64_to_cpu(desc_hw->m0) == in xgene_dma_cleanup_descriptors()
718 desc_hw->m0)), in xgene_dma_cleanup_descriptors()
720 desc_hw->m0))); in xgene_dma_cleanup_descriptors()
743 desc_hw->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE); in xgene_dma_cleanup_descriptors()
1097 desc->m0 = cpu_to_le64(XGENE_DMA_DESC_EMPTY_SIGNATURE); in xgene_dma_setup_ring()
/drivers/pwm/
A Dpwm-fsl-ftm.c153 enum fsl_pwm_clk m0, m1; in fsl_pwm_calculate_period() local
166 m0 = FSL_PWM_CLK_FIX; in fsl_pwm_calculate_period()
169 m0 = FSL_PWM_CLK_EXT; in fsl_pwm_calculate_period()
173 ret = fsl_pwm_calculate_period_clk(fpc, period_ns, m0, periodcfg); in fsl_pwm_calculate_period()
/drivers/net/ethernet/apm/xgene/
A Dxgene_enet_main.c32 raw_desc->m0 = cpu_to_le64(i | in xgene_enet_init_bufpool()
238 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); in xgene_enet_tx_completion()
261 status = GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); in xgene_enet_tx_completion()
540 raw_desc->m0 = cpu_to_le64(SET_VAL(LL, ll) | SET_VAL(NV, nv) | in xgene_enet_setup_tx_desc()
621 (!GET_VAL(NV, le64_to_cpu(raw_desc->m0)))) in xgene_enet_free_pagepool()
694 skb_index = GET_VAL(USERINFO, le64_to_cpu(raw_desc->m0)); in xgene_enet_rx_frame()
701 nv = GET_VAL(NV, le64_to_cpu(raw_desc->m0)); in xgene_enet_rx_frame()
710 status = (GET_VAL(ELERR, le64_to_cpu(raw_desc->m0)) << LERR_LEN) | in xgene_enet_rx_frame()
711 GET_VAL(LERR, le64_to_cpu(raw_desc->m0)); in xgene_enet_rx_frame()
780 return GET_VAL(FPQNUM, le64_to_cpu(raw_desc->m0)) ? true : false; in is_rx_desc()
[all …]
A Dxgene_enet_hw.h323 __le64 m0; member
330 __le64 m0; member
/drivers/staging/media/ipu3/
A Dipu3-css.c713 const enum imgu_abi_memories m0 = IMGU_ABI_MEM_ISP_DMEM0; in imgu_css_pipeline_init() local
715 void *vaddr = css_pipe->binary_params_cs[cfg - 1][m0].vaddr; in imgu_css_pipeline_init()
723 cfg_iter = imgu_css_fw_pipeline_params(css, pipe, cfg, m0, in imgu_css_pipeline_init()
772 cfg_ref = imgu_css_fw_pipeline_params(css, pipe, cfg, m0, in imgu_css_pipeline_init()
802 cfg_dvs = imgu_css_fw_pipeline_params(css, pipe, cfg, m0, in imgu_css_pipeline_init()
818 cfg_tnr = imgu_css_fw_pipeline_params(css, pipe, cfg, m0, in imgu_css_pipeline_init()
847 vaddr = css_pipe->binary_params_cs[cfg - 1][m0].vaddr; in imgu_css_pipeline_init()
849 cfg_ref_state = imgu_css_fw_pipeline_params(css, pipe, cfg, m0, in imgu_css_pipeline_init()
862 imgu_css_fw_pipeline_params(css, pipe, cfg, m0, in imgu_css_pipeline_init()
/drivers/net/wireless/broadcom/b43/
A Dphy_lcn.c198 static void b43_phy_lcn_set_bbmult(struct b43_wldev *dev, u8 m0) in b43_phy_lcn_set_bbmult() argument
200 b43_lcntab_write(dev, B43_LCNTAB16(0x00, 0x57), m0 << 8); in b43_phy_lcn_set_bbmult()
/drivers/net/wireless/realtek/rtw89/
A Dcam.h365 __le32 m0; member
442 __le32 m0; member
A Dcam.c981 h2c->m0 = cpu_to_le32(DCTLINFO_V1_W0_AES_IV_L); in rtw89_cam_fill_dctl_sec_cam_info_v1()
1071 h2c->m0 = cpu_to_le32(DCTLINFO_V2_W0_AES_IV_L); in rtw89_cam_fill_dctl_sec_cam_info_v2()
/drivers/net/ethernet/freescale/enetc/
A Denetc_qos.c318 u32 m0, ma, r0, ra; in enetc_setup_tc_cbs() local
320 m0 = port_frame_max_size * 8; in enetc_setup_tc_cbs()
325 max_interference_size = m0 + ma + in enetc_setup_tc_cbs()
326 (u32)div_u64((u64)ra * m0, r0 - ra); in enetc_setup_tc_cbs()
/drivers/clk/
A Dclk-versaclock7.c236 u64 m0 = a0 * b0; in vc7_64_mul_64_to_128() local
241 m2 += (m0 >> 32); in vc7_64_mul_64_to_128()
248 *lo = (m0 & 0xffffffffull) | (m2 << 32); in vc7_64_mul_64_to_128()
/drivers/acpi/nfit/
A Dcore.c2214 static int cmp_map_compat(const void *m0, const void *m1) in cmp_map_compat() argument
2216 const struct nfit_set_info *map0 = m0; in cmp_map_compat()
2223 static int cmp_map(const void *m0, const void *m1) in cmp_map() argument
2225 const struct nfit_set_info *map0 = m0; in cmp_map()
2235 static int cmp_map2(const void *m0, const void *m1) in cmp_map2() argument
2237 const struct nfit_set_info2 *map0 = m0; in cmp_map2()
/drivers/md/
A Ddm-raid1.c185 struct mirror *m0 = &(ms->mirror[0]); in set_default_mirror() local
187 atomic_set(&ms->default_mirror, m - m0); in set_default_mirror()
/drivers/pinctrl/
A Dpinctrl-th1520.c150 #define TH1520_PAD(_nr, _name, m0, m1, m2, m3, m4, m5, _flags) \ argument
152 (TH1520_MUX_##m0 << 0) | (TH1520_MUX_##m1 << 5) | (TH1520_MUX_##m2 << 10) | \

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