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Searched refs:m1 (Results 1 – 25 of 75) sorted by relevance

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/drivers/net/ethernet/broadcom/bnx2x/
A Dbnx2x_fw_defs.h25 (IRO[163].base + ((funcId) * IRO[163].m1))
27 (IRO[153].base + ((funcId) * IRO[153].m1))
35 (IRO[324].base + ((pfId) * IRO[324].m1))
37 (IRO[325].base + ((pfId) * IRO[325].m1))
53 (IRO[323].base + ((pfId) * IRO[323].m1))
55 (IRO[315].base + ((pfId) * IRO[315].m1))
57 (IRO[314].base + ((pfId) * IRO[314].m1))
59 (IRO[313].base + ((pfId) * IRO[313].m1))
63 (IRO[146].base + ((pfId) * IRO[146].m1))
65 (IRO[147].base + ((pfId) * IRO[147].m1))
[all …]
A Dbnx2x_init.h539 #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \ argument
543 en_mask, {m1, m1h, m2, m3}, #block \
546 #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \ argument
550 en_mask, {m1, m1h, m2, m3}, #block"_0" \
553 #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \ argument
557 en_mask, {m1, m1h, m2, m3}, #block"_1" \
/drivers/net/ethernet/qlogic/qed/
A Dqed_iro_hsi.h108 + ((pf_id) * IRO[IRO_ETH_RX_RATE_LIMIT].m1))
120 + ((pf_id) * IRO[IRO_MSTORM_ETH_PF_STAT].m1))
128 + ((vf_id) * IRO[IRO_MSTORM_ETH_VF_PRODS].m1) \
180 + ((pf_id) * IRO[IRO_PSTORM_ETH_PF_STAT].m1))
186 + ((pf_id) * IRO[IRO_PSTORM_FCOE_TX_STATS].m1))
295 + ((port_id) * IRO[IRO_TSTORM_PORT_STAT].m1))
343 + ((pf_id) * IRO[IRO_USTORM_EQE_CONS_GTT].m1))
349 + ((pf_id) * IRO[IRO_USTORM_ETH_PF_STAT].m1))
399 + ((rss_id) * IRO[IRO_USTORM_TOE_CQ_PROD].m1))
405 + ((pf_id) * IRO[IRO_USTORM_TOE_GRQ_PROD].m1))
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
A Dbwc_complex.c503 bool m1[MLX5HWS_DEFINER_FNAME_MAX] = {0}; in hws_bwc_matcher_complex_params_comb_is_valid() local
511 m1[fc[i].fname] = true; in hws_bwc_matcher_complex_params_comb_is_valid()
521 if (m1[MLX5HWS_DEFINER_FNAME_IP_FRAG_O] && in hws_bwc_matcher_complex_params_comb_is_valid()
535 if (m1[MLX5HWS_DEFINER_FNAME_IP_FRAG_I] && in hws_bwc_matcher_complex_params_comb_is_valid()
594 if ((m1[MLX5HWS_DEFINER_FNAME_GRE_C] || in hws_bwc_matcher_complex_params_comb_is_valid()
595 m1[MLX5HWS_DEFINER_FNAME_GRE_K] || in hws_bwc_matcher_complex_params_comb_is_valid()
596 m1[MLX5HWS_DEFINER_FNAME_GRE_S] || in hws_bwc_matcher_complex_params_comb_is_valid()
605 if ((m1[MLX5HWS_DEFINER_FNAME_TCP_ACK_NUM] || in hws_bwc_matcher_complex_params_comb_is_valid()
606 m1[MLX5HWS_DEFINER_FNAME_TCP_SEQ_NUM]) && in hws_bwc_matcher_complex_params_comb_is_valid()
636 struct mlx5hws_match_parameters *m1, in hws_bwc_matcher_complex_params_comb_create() argument
[all …]
/drivers/gpu/drm/i915/display/
A Dintel_dpll.c38 } dot, vco, n, m, m1, m2, p, p1; member
50 .m1 = { .min = 18, .max = 26 },
591 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in intel_pll_is_valid()
668 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in i9xx_find_best_dpll()
669 clock.m1++) { in i9xx_find_best_dpll()
726 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; in pnv_find_best_dpll()
727 clock.m1++) { in pnv_find_best_dpll()
789 for (clock.m1 = limit->m1.max; in g4x_find_best_dpll()
790 clock.m1 >= limit->m1.min; clock.m1--) { in g4x_find_best_dpll()
884 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in vlv_find_best_dpll()
[all …]
A Dvlv_dpio_phy_regs.h43 #define DPIO_M1_DIV(m1) REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1)) argument
195 #define DPIO_CHV_M1_DIV(m1) REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1)) argument
A Dg4x_dp.c36 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
37 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
41 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
42 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
46 { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
47 { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
52 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
53 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
/drivers/clk/meson/
A Dclk-dualdiv.c43 return DIV_ROUND_CLOSEST(parent_rate * (p->m1 + p->m2), in __dualdiv_param_to_rate()
44 p->n1 * p->m1 + p->n2 * p->m2); in __dualdiv_param_to_rate()
56 setting.m1 = meson_parm_read(clk->map, &dualdiv->m1) + 1; in meson_clk_dualdiv_recalc_rate()
121 meson_parm_write(clk->map, &dualdiv->m1, setting->m1 - 1); in meson_clk_dualdiv_set_rate()
A Dclk-dualdiv.h16 unsigned int m1; member
24 struct parm m1; member
A Dg12a-aoclk.c98 .m1 = 8,
133 .m1 = {
224 .m1 = {
/drivers/net/ethernet/netronome/nfp/flower/
A Dconntrack.h18 char *k1, *m1, *k2, *m2; \
21 m1 = (char *)_match1.mask; \
25 if ((k1[i] & m1[i] & m2[i]) ^ \
26 (k2[i] & m1[i] & m2[i])) { \
/drivers/gpu/drm/gma500/
A Dgma_display.c729 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) in gma_pll_is_valid()
732 if (clock->m1 <= clock->m2 && clock->m1 != 0) in gma_pll_is_valid()
783 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { in gma_find_best_pll()
785 (clock.m2 < clock.m1 || clock.m1 == 0) && in gma_find_best_pll()
A Dcdv_intel_display.c41 .m1 = {.min = 0, .max = 0},
53 .m1 = {.min = 0, .max = 0},
68 .m1 = {.min = 0, .max = 0},
80 .m1 = {.min = 0, .max = 0},
92 .m1 = {.min = 0, .max = 0},
104 .m1 = {.min = 0, .max = 0},
417 clock.m1 = 0; in cdv_intel_find_dp_pll()
423 clock.m1 = 0; in cdv_intel_find_dp_pll()
433 clock.m1 = 0; in cdv_intel_find_dp_pll()
439 clock.m1 = 0; in cdv_intel_find_dp_pll()
[all …]
A Dgma_display.h22 int m1, m2; member
41 struct gma_range_t dot, vco, n, m, m1, m2, p, p1; member
A Dpsb_intel_display.c32 .m1 = {.min = 8, .max = 18},
44 .m1 = {.min = 8, .max = 18},
70 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
156 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; in psb_intel_crtc_mode_set()
336 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; in psb_intel_crtc_clock_get()
/drivers/gpu/drm/nouveau/dispnv04/
A Darb.c58 int found, mclk_extra, mclk_loop, cbs, m1, p1; in nv04_calc_arb() local
92 m1 = clwm + cbs - 512; in nv04_calc_arb()
93 p1 = m1 * pclk_freq / mclk_freq; in nv04_calc_arb()
95 if ((p1 < m1 && m1 > 0) || clwm > 519) { in nv04_calc_arb()
/drivers/ssb/
A Dmain.c848 u32 n1, n2, clock, m1, m2, m3, mc; in ssb_calc_clock_rate() local
888 m1 = (m & SSB_CHIPCO_CLK_M1); in ssb_calc_clock_rate()
898 m1 = clkfactor_f6_resolve(m1); in ssb_calc_clock_rate()
910 return (clock / m1); in ssb_calc_clock_rate()
912 return (clock / (m1 * m2)); in ssb_calc_clock_rate()
914 return (clock / (m1 * m2 * m3)); in ssb_calc_clock_rate()
916 return (clock / (m1 * m3)); in ssb_calc_clock_rate()
920 m1 += SSB_CHIPCO_CLK_T2_BIAS; in ssb_calc_clock_rate()
923 WARN_ON(!((m1 >= 2) && (m1 <= 7))); in ssb_calc_clock_rate()
928 clock /= m1; in ssb_calc_clock_rate()
/drivers/media/common/saa7146/
A Dsaa7146_video.c107 int i, m1, m2, m3, o1, o2; in saa7146_pgtable_build() local
112 m1 = ((size + PAGE_SIZE) / PAGE_SIZE) - 1; in saa7146_pgtable_build()
118 size, m1, m2, m3, o1, o2); in saa7146_pgtable_build()
123 m1 = ((size + PAGE_SIZE) / PAGE_SIZE) - 1; in saa7146_pgtable_build()
129 size, m1, m2, m3, o1, o2); in saa7146_pgtable_build()
152 for (i = m1; i <= m2; i++, ptr2++) in saa7146_pgtable_build()
165 ptr1 = pt1->cpu + m1; in saa7146_pgtable_build()
166 fill = pt1->cpu[m1]; in saa7146_pgtable_build()
167 for (i = m1; i < 1024; i++, ptr1++) in saa7146_pgtable_build()
/drivers/net/ethernet/apm/xgene-v2/
A Dmain.c94 addr_hi = GET_BITS(NEXT_DESC_ADDRH, le64_to_cpu(raw_desc->m1)); in xge_refill_buffers()
95 addr_lo = GET_BITS(NEXT_DESC_ADDRL, le64_to_cpu(raw_desc->m1)); in xge_refill_buffers()
96 raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, addr_lo) | in xge_refill_buffers()
201 addr_hi = GET_BITS(NEXT_DESC_ADDRH, le64_to_cpu(raw_desc->m1)); in xge_start_xmit()
202 addr_lo = GET_BITS(NEXT_DESC_ADDRL, le64_to_cpu(raw_desc->m1)); in xge_start_xmit()
203 raw_desc->m1 = cpu_to_le64(SET_BITS(NEXT_DESC_ADDRL, addr_lo) | in xge_start_xmit()
/drivers/net/wireless/intel/iwlegacy/
A D4965.c672 const struct il_eeprom_calib_measure *m1; in il4965_interpolate_chan() local
693 m1 = &(il->calib_info->band_info[s].ch1. in il4965_interpolate_chan()
701 m1->actual_pow, ch_i2, in il4965_interpolate_chan()
705 m1->gain_idx, ch_i2, in il4965_interpolate_chan()
709 m1->temperature, in il4965_interpolate_chan()
714 m1->pa_det, ch_i2, in il4965_interpolate_chan()
718 m, m1->actual_pow, m2->actual_pow, in il4965_interpolate_chan()
721 m, m1->gain_idx, m2->gain_idx, in il4965_interpolate_chan()
724 m, m1->pa_det, m2->pa_det, omeas->pa_det); in il4965_interpolate_chan()
726 m, m1->temperature, m2->temperature, in il4965_interpolate_chan()
/drivers/media/cec/platform/meson/
A Dao-cec-g12a.c238 unsigned long n2, m1, m2, f1, f2, p1, p2; in meson_ao_cec_g12a_dualdiv_clk_recalc_rate() local
243 m1 = FIELD_GET(CECB_CLK_CNTL_M1, reg1) + 1; in meson_ao_cec_g12a_dualdiv_clk_recalc_rate()
249 p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2)); in meson_ao_cec_g12a_dualdiv_clk_recalc_rate()
250 p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2)); in meson_ao_cec_g12a_dualdiv_clk_recalc_rate()
/drivers/pwm/
A Dpwm-fsl-ftm.c153 enum fsl_pwm_clk m0, m1; in fsl_pwm_calculate_period() local
167 m1 = FSL_PWM_CLK_EXT; in fsl_pwm_calculate_period()
170 m1 = FSL_PWM_CLK_FIX; in fsl_pwm_calculate_period()
177 return fsl_pwm_calculate_period_clk(fpc, period_ns, m1, periodcfg); in fsl_pwm_calculate_period()
/drivers/usb/mon/
A Dmon_main.c45 struct mon_bus *m1; in mon_reader_add() local
46 m1 = list_entry(p, struct mon_bus, bus_link); in mon_reader_add()
47 m1->u_bus->monitored = 1; in mon_reader_add()
/drivers/i2c/busses/
A Di2c-sh7760.c395 unsigned long mck, m1, dff, odff, iclk; in calc_CCR() local
408 scgdm = cdfm = m1 = 0; in calc_CCR()
415 m1 = iclk / (20 + (scgd << 3)); in calc_CCR()
416 dff = abs(scl_hz - m1); in calc_CCR()
/drivers/media/pci/ttpci/
A Dbudget-av.c467 u8 m1; in philips_su1278_ty_ci_set_symbol_rate() local
479 m1 = 0x14; in philips_su1278_ty_ci_set_symbol_rate()
481 m1 = 0x10; in philips_su1278_ty_ci_set_symbol_rate()
488 stv0299_writereg(fe, 0x0f, 0x80 | m1); in philips_su1278_ty_ci_set_symbol_rate()
840 u8 m1; in philips_sd1878_ci_set_symbol_rate() local
852 m1 = 0x14; in philips_sd1878_ci_set_symbol_rate()
854 m1 = 0x10; in philips_sd1878_ci_set_symbol_rate()
865 stv0299_writereg(fe, 0x0f, 0x80 | m1); in philips_sd1878_ci_set_symbol_rate()

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