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Searched refs:m2 (Results 1 – 25 of 68) sorted by relevance

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/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
A Dbwc_complex.c504 bool m2[MLX5HWS_DEFINER_FNAME_MAX] = {0}; in hws_bwc_matcher_complex_params_comb_is_valid() local
513 m2[fc[i].fname] = true; in hws_bwc_matcher_complex_params_comb_is_valid()
528 if (m2[MLX5HWS_DEFINER_FNAME_IP_FRAG_O] && in hws_bwc_matcher_complex_params_comb_is_valid()
542 if (m2[MLX5HWS_DEFINER_FNAME_IP_FRAG_I] && in hws_bwc_matcher_complex_params_comb_is_valid()
598 (m2[MLX5HWS_DEFINER_FNAME_GRE_C] || in hws_bwc_matcher_complex_params_comb_is_valid()
599 m2[MLX5HWS_DEFINER_FNAME_GRE_K] || in hws_bwc_matcher_complex_params_comb_is_valid()
600 m2[MLX5HWS_DEFINER_FNAME_GRE_S] || in hws_bwc_matcher_complex_params_comb_is_valid()
608 m2[MLX5HWS_DEFINER_FNAME_TCP_SEQ_NUM])) in hws_bwc_matcher_complex_params_comb_is_valid()
637 struct mlx5hws_match_parameters *m2, in hws_bwc_matcher_complex_params_comb_create() argument
653 m2 : m1); in hws_bwc_matcher_complex_params_comb_create()
[all …]
/drivers/gpu/drm/i915/display/
A Dintel_dpll.c51 .m2 = { .min = 6, .max = 16 },
320 clock->m = clock->m2 + 2; in pnv_calc_dpll_params()
589 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in intel_pll_is_valid()
670 for (clock.m2 = limit->m2.min; in i9xx_find_best_dpll()
671 clock.m2 <= limit->m2.max; clock.m2++) { in i9xx_find_best_dpll()
728 for (clock.m2 = limit->m2.min; in pnv_find_best_dpll()
729 clock.m2 <= limit->m2.max; clock.m2++) { in pnv_find_best_dpll()
791 for (clock.m2 = limit->m2.max; in g4x_find_best_dpll()
792 clock.m2 >= limit->m2.min; clock.m2--) { in g4x_find_best_dpll()
928 u64 m2; in chv_find_best_dpll() local
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A Dvlv_dpio_phy_regs.h45 #define DPIO_M2_DIV(m2) REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2)) argument
189 #define DPIO_CHV_M2_DIV(m2) REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2)) argument
A Dg4x_dp.c36 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8, },
37 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2, },
41 { .dot = 162000, .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9, },
42 { .dot = 270000, .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8, },
46 { .dot = 162000, .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81, },
47 { .dot = 270000, .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27, },
52 { .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
53 { .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
/drivers/video/fbdev/omap2/omapfb/dss/
A Dhdmi_pll.c45 unsigned n, m, mf, m2, sd; in hdmi_pll_compute() local
61 m2 = DIV_ROUND_UP(min_dco, target_bitclk); in hdmi_pll_compute()
62 if (m2 == 0) in hdmi_pll_compute()
63 m2 = 1; in hdmi_pll_compute()
65 target_clkdco = target_bitclk * m2; in hdmi_pll_compute()
79 clkout = clkdco / m2; in hdmi_pll_compute()
85 n, m, mf, m2, sd); in hdmi_pll_compute()
91 pi->mX[0] = m2; in hdmi_pll_compute()
/drivers/net/ethernet/broadcom/bnx2x/
A Dbnx2x_fw_defs.h20 IRO[157].m2))
23 IRO[158].m2))
29 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
32 * IRO[142].m2) + ((sbId) * IRO[142].m3))
39 (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
41 (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
43 (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
73 (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
79 (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
172 IRO[216].m2))
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A Dbnx2x_init.h539 #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \ argument
543 en_mask, {m1, m1h, m2, m3}, #block \
546 #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \ argument
550 en_mask, {m1, m1h, m2, m3}, #block"_0" \
553 #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \ argument
557 en_mask, {m1, m1h, m2, m3}, #block"_1" \
/drivers/clk/meson/
A Dclk-dualdiv.c43 return DIV_ROUND_CLOSEST(parent_rate * (p->m1 + p->m2), in __dualdiv_param_to_rate()
44 p->n1 * p->m1 + p->n2 * p->m2); in __dualdiv_param_to_rate()
58 setting.m2 = meson_parm_read(clk->map, &dualdiv->m2) + 1; in meson_clk_dualdiv_recalc_rate()
123 meson_parm_write(clk->map, &dualdiv->m2, setting->m2 - 1); in meson_clk_dualdiv_set_rate()
A Dclk-dualdiv.h17 unsigned int m2; member
25 struct parm m2; member
A Dg12a-aoclk.c100 .m2 = 11,
138 .m2 = {
229 .m2 = {
A Dgxbb-aoclk.c84 .m2 = 11,
105 .m2 = {
A Daxg-aoclk.c98 .m2 = 11,
119 .m2 = {
/drivers/gpu/drm/gma500/
A Dcdv_intel_display.c42 .m2 = {.min = 58, .max = 158},
54 .m2 = {.min = 58, .max = 158},
69 .m2 = {.min = 65, .max = 130},
81 .m2 = {.min = 58, .max = 158},
93 .m2 = {.min = 65, .max = 130},
105 .m2 = {.min = 58, .max = 162},
395 clock->m = clock->m2 + 2; in cdv_intel_clock()
418 clock.m2 = 118; in cdv_intel_find_dp_pll()
424 clock.m2 = 98; in cdv_intel_find_dp_pll()
434 clock.m2 = 160; in cdv_intel_find_dp_pll()
[all …]
A Dgma_display.c727 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) in gma_pll_is_valid()
732 if (clock->m1 <= clock->m2 && clock->m1 != 0) in gma_pll_is_valid()
784 for (clock.m2 = limit->m2.min; in gma_find_best_pll()
785 (clock.m2 < clock.m1 || clock.m1 == 0) && in gma_find_best_pll()
786 clock.m2 <= limit->m2.max; clock.m2++) { in gma_find_best_pll()
A Dgma_display.h22 int m1, m2; member
41 struct gma_range_t dot, vco, n, m, m1, m2, p, p1; member
A Dpsb_intel_display.c33 .m2 = {.min = 3, .max = 7},
45 .m2 = {.min = 3, .max = 7},
70 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2); in psb_intel_clock()
156 fp = clock.n << 16 | clock.m1 << 8 | clock.m2; in psb_intel_crtc_mode_set()
337 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; in psb_intel_crtc_clock_get()
/drivers/net/ethernet/netronome/nfp/flower/
A Dconntrack.h18 char *k1, *m1, *k2, *m2; \
23 m2 = (char *)_match2.mask; \
25 if ((k1[i] & m1[i] & m2[i]) ^ \
26 (k2[i] & m1[i] & m2[i])) { \
/drivers/gpu/drm/omapdrm/dss/
A Dpll.c278 unsigned int n, m, mf, m2, sd; in dss_pll_calc_b() local
289 m2 = DIV_ROUND_UP(min_dco, target_clkout); in dss_pll_calc_b()
290 if (m2 == 0) in dss_pll_calc_b()
291 m2 = 1; in dss_pll_calc_b()
293 target_clkdco = target_clkout * m2; in dss_pll_calc_b()
307 clkout = clkdco / m2; in dss_pll_calc_b()
313 n, m, mf, m2, sd); in dss_pll_calc_b()
319 cinfo->mX[0] = m2; in dss_pll_calc_b()
/drivers/ssb/
A Dmain.c848 u32 n1, n2, clock, m1, m2, m3, mc; in ssb_calc_clock_rate() local
889 m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT); in ssb_calc_clock_rate()
901 m2 += SSB_CHIPCO_CLK_F5_BIAS; in ssb_calc_clock_rate()
903 m2 = clkfactor_f6_resolve(m2); in ssb_calc_clock_rate()
912 return (clock / (m1 * m2)); in ssb_calc_clock_rate()
914 return (clock / (m1 * m2 * m3)); in ssb_calc_clock_rate()
921 m2 += SSB_CHIPCO_CLK_T2M2_BIAS; in ssb_calc_clock_rate()
924 WARN_ON(!((m2 >= 3) && (m2 <= 10))); in ssb_calc_clock_rate()
930 clock /= m2; in ssb_calc_clock_rate()
/drivers/media/common/saa7146/
A Dsaa7146_video.c107 int i, m1, m2, m3, o1, o2; in saa7146_pgtable_build() local
113 m2 = ((size + (size / 4) + PAGE_SIZE) / PAGE_SIZE) - 1; in saa7146_pgtable_build()
118 size, m1, m2, m3, o1, o2); in saa7146_pgtable_build()
124 m2 = ((size + (size / 2) + PAGE_SIZE) / PAGE_SIZE) - 1; in saa7146_pgtable_build()
129 size, m1, m2, m3, o1, o2); in saa7146_pgtable_build()
152 for (i = m1; i <= m2; i++, ptr2++) in saa7146_pgtable_build()
159 for (i = m2; i <= m3; i++, ptr3++) in saa7146_pgtable_build()
/drivers/net/wireless/intel/iwlegacy/
A D4965.c673 const struct il_eeprom_calib_measure *m2; in il4965_interpolate_chan() local
695 m2 = &(il->calib_info->band_info[s].ch2. in il4965_interpolate_chan()
702 m2->actual_pow); in il4965_interpolate_chan()
706 m2->gain_idx); in il4965_interpolate_chan()
711 m2->temperature); in il4965_interpolate_chan()
715 m2->pa_det); in il4965_interpolate_chan()
718 m, m1->actual_pow, m2->actual_pow, in il4965_interpolate_chan()
721 m, m1->gain_idx, m2->gain_idx, in il4965_interpolate_chan()
724 m, m1->pa_det, m2->pa_det, omeas->pa_det); in il4965_interpolate_chan()
726 m, m1->temperature, m2->temperature, in il4965_interpolate_chan()
/drivers/media/cec/platform/meson/
A Dao-cec-g12a.c238 unsigned long n2, m1, m2, f1, f2, p1, p2; in meson_ao_cec_g12a_dualdiv_clk_recalc_rate() local
244 m2 = FIELD_GET(CECB_CLK_CNTL_M1, reg1) + 1; in meson_ao_cec_g12a_dualdiv_clk_recalc_rate()
249 p1 = DIV_ROUND_CLOSEST(100000000 * m1, f1 * (m1 + m2)); in meson_ao_cec_g12a_dualdiv_clk_recalc_rate()
250 p2 = DIV_ROUND_CLOSEST(100000000 * m2, f2 * (m1 + m2)); in meson_ao_cec_g12a_dualdiv_clk_recalc_rate()
/drivers/ata/
A Dahci_imx.c300 int m1, m2, a; in __sata_ahci_read_temperature() local
357 m2 = read_adc_sum(dev, rtune_ctl_reg, mmio); in __sata_ahci_read_temperature()
377 if (!(m2 / 1000)) in __sata_ahci_read_temperature()
378 m2 = 1000; in __sata_ahci_read_temperature()
379 a = (m2 - m1) / (m2/1000); in __sata_ahci_read_temperature()
/drivers/input/touchscreen/
A Dmxs-lradc-ts.c228 unsigned int pressure, m1, m2; in mxs_lradc_read_ts_pressure() local
239 m2 = mxs_lradc_ts_read_raw_channel(ts, ch2); in mxs_lradc_read_ts_pressure()
241 if (m2 == 0) { in mxs_lradc_read_ts_pressure()
249 pressure /= m2; in mxs_lradc_read_ts_pressure()
/drivers/scsi/
A Dmvumi.h398 int size, m1, m2; \
400 m2 = max(HSP_SIZE(2), HSP_SIZE(4)); \
401 size = max(m1, m2); \

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