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Searched refs:m_frac (Results 1 – 2 of 2) sorted by relevance

/drivers/clk/
A Dclk-si514.c55 u32 m_frac; /* 29-bit Fractional part of multiplier M */ member
107 settings->m_frac = reg[0] | reg[1] << 8 | reg[2] << 16 | in si514_get_muldiv()
125 (settings->m_int == 65 && settings->m_frac <= 139575831)) in si514_set_muldiv()
129 (settings->m_int == 67 && settings->m_frac <= 461581994)) in si514_set_muldiv()
133 (settings->m_int == 72 && settings->m_frac <= 503383578)) in si514_set_muldiv()
146 reg[0] = settings->m_frac; in si514_set_muldiv()
147 reg[1] = settings->m_frac >> 8; in si514_set_muldiv()
148 reg[2] = settings->m_frac >> 16; in si514_set_muldiv()
149 reg[3] = settings->m_frac >> 24 | settings->m_int << 5; in si514_set_muldiv()
199 settings->m_frac = (u32)m & (BIT(29) - 1); in si514_calc_muldiv()
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/drivers/clk/xilinx/
A Dclk-xlnx-clock-wizard.c173 u32 m_frac; member
407 divider->m_frac = (m - (divider->m << 3)) * 125; in clk_wzrd_get_divisors()
520 FIELD_PREP(WZRD_CLKFBOUT_MULT_FRAC_MASK, divider->m_frac) | in clk_wzrd_dynamic_all_nolock()
660 rate = div_u64(*prate * (m * 1000 + divider->m_frac), d * (o * 1000 + divider->o_frac)); in clk_wzrd_round_rate_all()

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