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/drivers/accel/habanalabs/gaudi/
A Dgaudi_security.c489 u32 pb_addr, mask; in gaudi_init_mme_protection_bits() local
546 WREG32(pb_addr + word_offset, ~mask); in gaudi_init_mme_protection_bits()
553 WREG32(pb_addr + word_offset, ~mask); in gaudi_init_mme_protection_bits()
587 WREG32(pb_addr + word_offset, ~mask); in gaudi_init_mme_protection_bits()
624 WREG32(pb_addr + word_offset, ~mask); in gaudi_init_mme_protection_bits()
644 WREG32(pb_addr + word_offset, ~mask); in gaudi_init_mme_protection_bits()
677 WREG32(pb_addr + word_offset, ~mask); in gaudi_init_mme_protection_bits()
714 WREG32(pb_addr + word_offset, ~mask); in gaudi_init_mme_protection_bits()
1473 u32 pb_addr, mask; in gaudi_init_dma_protection_bits() local
5189 u32 pb_addr, mask; in gaudi_init_nic_protection_bits() local
[all …]
/drivers/accel/habanalabs/goya/
A Dgoya_security.c30 u32 pb_addr, mask; in goya_init_mme_protection_bits() local
81 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
86 mask |= 1 << ((mmMME_AGU & 0x7F) >> 2); in goya_init_mme_protection_bits()
95 mask |= 1 << ((mmMME_TE & 0x7F) >> 2); in goya_init_mme_protection_bits()
104 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
128 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
160 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
180 WREG32(pb_addr + word_offset, ~mask); in goya_init_mme_protection_bits()
274 u32 pb_addr, mask; in goya_init_dma_protection_bits() local
674 u32 pb_addr, mask; in goya_init_tpc_protection_bits() local
[all …]
/drivers/video/fbdev/riva/
A Dnvreg.h31 #define MASKEXPAND(mask) BITMASK(1?mask,0?mask) argument
34 #define SetBF(mask,value) ((value) << (0?mask)) argument
35 #define GetBF(var,mask) (((unsigned)((var) & MASKEXPAND(mask))) >> (0?mask) ) argument
52 SetBF(NV_##device##_##mask,NV_##device##_##mask##_##value)
61 #define PDAC_Mask(mask) DEVICE_MASK(PDAC,mask) argument
68 #define PFB_Mask(mask) DEVICE_MASK(PFB,mask) argument
75 #define PRM_Mask(mask) DEVICE_MASK(PRM,mask) argument
89 #define PDMA_Mask(mask) DEVICE_MASK(PDMA,mask) argument
131 #define PMC_Mask(mask) DEVICE_MASK(PMC,mask) argument
138 #define PMC_Mask(mask) DEVICE_MASK(PMC,mask) argument
[all …]
/drivers/net/ethernet/chelsio/cxgb4/
A Dcxgb4_tc_u32_parse.h49 f->mask.tos = (ntohl(mask) >> 16) & 0x000000FF; in cxgb4_fill_ipv4_tos()
89 memcpy(&f->mask.fip[0], &mask, sizeof(u32)); in cxgb4_fill_ipv4_src_ip()
98 memcpy(&f->mask.lip[0], &mask, sizeof(u32)); in cxgb4_fill_ipv4_dst_ip()
135 memcpy(&f->mask.fip[0], &mask, sizeof(u32)); in cxgb4_fill_ipv6_src_ip0()
144 memcpy(&f->mask.fip[4], &mask, sizeof(u32)); in cxgb4_fill_ipv6_src_ip1()
153 memcpy(&f->mask.fip[8], &mask, sizeof(u32)); in cxgb4_fill_ipv6_src_ip2()
171 memcpy(&f->mask.lip[0], &mask, sizeof(u32)); in cxgb4_fill_ipv6_dst_ip0()
180 memcpy(&f->mask.lip[4], &mask, sizeof(u32)); in cxgb4_fill_ipv6_dst_ip1()
189 memcpy(&f->mask.lip[8], &mask, sizeof(u32)); in cxgb4_fill_ipv6_dst_ip2()
222 f->mask.fport = ntohl(mask) >> 16; in cxgb4_fill_l4_ports()
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/steering/sws/
A Ddr_matcher.c422 mask.outer = matcher->mask.outer; in dr_matcher_set_ste_builders()
425 mask.misc = matcher->mask.misc; in dr_matcher_set_ste_builders()
428 mask.inner = matcher->mask.inner; in dr_matcher_set_ste_builders()
431 mask.misc2 = matcher->mask.misc2; in dr_matcher_set_ste_builders()
434 mask.misc3 = matcher->mask.misc3; in dr_matcher_set_ste_builders()
437 mask.misc4 = matcher->mask.misc4; in dr_matcher_set_ste_builders()
440 mask.misc5 = matcher->mask.misc5; in dr_matcher_set_ste_builders()
494 if (DR_MASK_IS_L2_DST(mask.outer, mask.misc, outer)) in dr_matcher_set_ste_builders()
507 if (DR_MASK_IS_ETH_L4_SET(mask.outer, mask.misc, outer)) in dr_matcher_set_ste_builders()
602 if (DR_MASK_IS_L2_DST(mask.inner, mask.misc, inner)) in dr_matcher_set_ste_builders()
[all …]
A Ddr_ste.c11 u8 mask[DR_STE_SIZE_MASK]; member
85 memset(&hw_ste->mask, 0, sizeof(hw_ste->mask)); in dr_ste_set_always_hit()
91 hw_ste->mask[0] = 0; in dr_ste_set_always_miss()
722 if (mask->misc.source_port && mask->misc.source_port != 0xffff) { in mlx5dr_ste_build_pre_check()
759 &matcher->mask, value); in mlx5dr_ste_build_ste_arr()
1031 u8 *data = (u8 *)mask->match_buf; in mlx5dr_ste_copy_param()
1040 buff = mask->match_buf; in mlx5dr_ste_copy_param()
1169 struct mlx5dr_match_param *mask, in mlx5dr_ste_build_eth_l2_src() argument
1179 struct mlx5dr_match_param *mask, in mlx5dr_ste_build_eth_l2_dst() argument
1238 ste_ctx->build_mpls_init(sb, mask); in mlx5dr_ste_build_mpls()
[all …]
/drivers/mfd/
A Dwm8350-irq.c37 int mask; member
45 .mask = WM8350_OC_LS_EINT,
51 .mask = WM8350_UV_DC1_EINT,
56 .mask = WM8350_UV_DC2_EINT,
61 .mask = WM8350_UV_DC3_EINT,
66 .mask = WM8350_UV_DC4_EINT,
166 .mask = WM8350_CS1_EINT,
171 .mask = WM8350_CS2_EINT,
297 .mask = WM8350_GP0_EINT,
302 .mask = WM8350_GP1_EINT,
[all …]
A Dwm831x-irq.c28 int mask; member
40 .mask = WM831X_GP1_EINT,
45 .mask = WM831X_GP2_EINT,
50 .mask = WM831X_GP3_EINT,
55 .mask = WM831X_GP4_EINT,
60 .mask = WM831X_GP5_EINT,
65 .mask = WM831X_GP6_EINT,
70 .mask = WM831X_GP7_EINT,
75 .mask = WM831X_GP8_EINT,
80 .mask = WM831X_GP9_EINT,
[all …]
A Dda9052-irq.c38 .mask = DA9052_IRQ_MASK_POS_1,
42 .mask = DA9052_IRQ_MASK_POS_2,
46 .mask = DA9052_IRQ_MASK_POS_3,
50 .mask = DA9052_IRQ_MASK_POS_4,
54 .mask = DA9052_IRQ_MASK_POS_5,
58 .mask = DA9052_IRQ_MASK_POS_6,
62 .mask = DA9052_IRQ_MASK_POS_7,
66 .mask = DA9052_IRQ_MASK_POS_8,
70 .mask = DA9052_IRQ_MASK_POS_1,
74 .mask = DA9052_IRQ_MASK_POS_2,
[all …]
A Dwm5110-tables.c285 .mask = ARIZONA_MICD_CLAMP_FALL_EINT1
288 .mask = ARIZONA_MICD_CLAMP_RISE_EINT1
328 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ8_EINT1
331 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ7_EINT1
334 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ6_EINT1
337 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ5_EINT1
340 .reg_offset = 1, .mask = ARIZONA_DSP_IRQ4_EINT1
359 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
362 .reg_offset = 2, .mask = ARIZONA_MICDET_EINT1
519 .reg_offset = 2, .mask = ARIZONA_HPDET_EINT1
[all …]
A Dpalmas.c48 .mask = TPS65917_RESERVED,
57 .mask = TPS65917_RESERVED,
69 .mask = TPS65917_RESERVED,
73 .mask = TPS65917_RESERVED,
85 .mask = TPS65917_RESERVED,
101 .mask = TPS65917_RESERVED,
118 .mask = TPS65917_RESERVED6,
122 .mask = TPS65917_RESERVED,
126 .mask = TPS65917_RESERVED,
130 .mask = TPS65917_RESERVED,
[all …]
/drivers/iio/imu/st_lsm6dsx/
A Dst_lsm6dsx_core.c124 .mask = BIT(0),
128 .mask = BIT(7),
132 .mask = BIT(6),
232 .mask = BIT(0),
236 .mask = BIT(7),
240 .mask = BIT(6),
398 .mask = BIT(0),
402 .mask = BIT(7),
1805 switch (mask) { in st_lsm6dsx_read_raw()
1841 switch (mask) { in st_lsm6dsx_write_raw()
[all …]
/drivers/platform/mellanox/
A Dmlx-platform.c703 .mask = BIT(0),
709 .mask = BIT(1),
719 .mask = BIT(0),
725 .mask = BIT(1),
734 .mask = BIT(0),
741 .mask = BIT(1),
751 .mask = BIT(0),
757 .mask = BIT(1),
766 .mask = BIT(0),
773 .mask = BIT(1),
[all …]
/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
A Dbwc_complex.c35 mask->match_buf, in mlx5hws_bwc_match_params_is_complex()
36 mask->match_sz, in mlx5hws_bwc_match_params_is_complex()
137 HWS_CLEAR_MATCH_PARAM(mask, in hws_bwc_matcher_complex_params_clear_fld()
139 HWS_CLEAR_MATCH_PARAM(mask, in hws_bwc_matcher_complex_params_clear_fld()
143 HWS_CLEAR_MATCH_PARAM(mask, in hws_bwc_matcher_complex_params_clear_fld()
145 HWS_CLEAR_MATCH_PARAM(mask, in hws_bwc_matcher_complex_params_clear_fld()
191 HWS_CLEAR_MATCH_PARAM(mask, in hws_bwc_matcher_complex_params_clear_fld()
195 HWS_CLEAR_MATCH_PARAM(mask, in hws_bwc_matcher_complex_params_clear_fld()
199 HWS_CLEAR_MATCH_PARAM(mask, in hws_bwc_matcher_complex_params_clear_fld()
703 mask->match_buf, in hws_bwc_matcher_complex_params_create()
[all …]
/drivers/iio/accel/
A Dst_accel_core.c128 .mask = 0xf0,
142 .mask = 0xf0,
151 .mask = 0x30,
177 .mask = 0x80,
210 .mask = 0x18,
220 .mask = 0xe0,
230 .mask = 0x30,
251 .mask = 0x80,
289 .mask = 0xf0,
305 .mask = 0xf0,
[all …]
/drivers/video/fbdev/
A Dc2p_core.h62 u32 mask = get_mask(n); in transp8() local
67 _transp(d, 0, 1, n, mask); in transp8()
69 _transp(d, 2, 3, n, mask); in transp8()
71 _transp(d, 4, 5, n, mask); in transp8()
73 _transp(d, 6, 7, n, mask); in transp8()
78 _transp(d, 0, 2, n, mask); in transp8()
79 _transp(d, 1, 3, n, mask); in transp8()
81 _transp(d, 4, 6, n, mask); in transp8()
82 _transp(d, 5, 7, n, mask); in transp8()
104 u32 mask = get_mask(n); in transp4() local
[all …]
/drivers/input/joystick/
A Danalog.c93 int mask; member
102 unsigned char mask; member
185 this = port->mask; in analog_cooked_read()
275 if (port->analog[i].mask) in analog_poll()
461 if (!port->mask) in analog_init_masks()
464 if ((port->mask & 3) != 3 && port->mask != 0xc) { in analog_init_masks()
477 | port->mask | ((port->mask << 8) & ANALOG_HAT_FCS) in analog_init_masks()
494 analog[1].mask &= (analog[0].mask & ANALOG_EXTENSIONS) ? ANALOG_GAMEPAD in analog_init_masks()
495 : (((ANALOG_BTNS_STD | port->mask) & ~analog[0].mask) | ANALOG_GAMEPAD); in analog_init_masks()
513 return -!(analog[0].mask || analog[1].mask); in analog_init_masks()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dce60/
A Dhw_translate_dce60.c48 uint32_t mask = 1; in index_from_vector() local
51 if (vector == mask) in index_from_vector()
55 mask <<= 1; in index_from_vector()
56 } while (mask); in index_from_vector()
65 uint32_t mask, in offset_to_id() argument
73 switch (mask) { in offset_to_id()
103 switch (mask) { in offset_to_id()
130 switch (mask) { in offset_to_id()
145 switch (mask) { in offset_to_id()
362 info->mask = in id_to_offset()
[all …]
/drivers/gpu/drm/amd/display/dc/gpio/dce80/
A Dhw_translate_dce80.c48 uint32_t mask = 1; in index_from_vector() local
51 if (vector == mask) in index_from_vector()
55 mask <<= 1; in index_from_vector()
56 } while (mask); in index_from_vector()
65 uint32_t mask, in offset_to_id() argument
73 switch (mask) { in offset_to_id()
103 switch (mask) { in offset_to_id()
130 switch (mask) { in offset_to_id()
145 switch (mask) { in offset_to_id()
362 info->mask = in id_to_offset()
[all …]
/drivers/media/pci/ivtv/
A Divtv-gpio.c151 mask = itv->card->gpio_audio_freq.mask; in subdev_s_clock_freq()
164 if (mask) in subdev_s_clock_freq()
172 u16 mask; in subdev_g_tuner() local
174 mask = itv->card->gpio_audio_detect.mask; in subdev_g_tuner()
188 mask = itv->card->gpio_audio_mode.mask; in subdev_s_tuner()
205 if (mask) in subdev_s_tuner()
215 mask = itv->card->gpio_audio_input.mask; in subdev_s_radio()
217 if (mask) in subdev_s_radio()
230 mask = itv->card->gpio_audio_input.mask; in subdev_s_audio_routing()
256 mask = itv->card->gpio_audio_mute.mask; in subdev_s_ctrl()
[all …]
/drivers/memory/tegra/
A Dtegra114.c22 .mask = 0xff,
38 .mask = 0xff,
54 .mask = 0xff,
70 .mask = 0xff,
86 .mask = 0xff,
102 .mask = 0xff,
118 .mask = 0xff,
134 .mask = 0xff,
150 .mask = 0xff,
166 .mask = 0xff,
[all …]
A Dtegra210.c27 .mask = 0xff,
43 .mask = 0xff,
59 .mask = 0xff,
75 .mask = 0xff,
91 .mask = 0xff,
107 .mask = 0xff,
123 .mask = 0xff,
139 .mask = 0xff,
155 .mask = 0xff,
171 .mask = 0xff,
[all …]
/drivers/soc/ixp4xx/
A Dixp4xx-qmgr.c232 mask[3] = mask[3] << 1 | mask[2] >> 31; in shift_mask()
233 mask[2] = mask[2] << 1 | mask[1] >> 31; in shift_mask()
234 mask[1] = mask[1] << 1 | mask[0] >> 31; in shift_mask()
235 mask[0] <<= 1; in shift_mask()
260 mask[0] = 0x1; in qmgr_request_queue()
264 mask[0] = 0x3; in qmgr_request_queue()
268 mask[0] = 0xF; in qmgr_request_queue()
272 mask[0] = 0xFF; in qmgr_request_queue()
281 mask[1] = mask[2] = mask[3] = 0; in qmgr_request_queue()
300 shift_mask(mask); in qmgr_request_queue()
[all …]
/drivers/pinctrl/spear/
A Dpinctrl-spear320.c36 .mask = 0x00000007,
44 .mask = 0x00000007,
52 .mask = 0x00000007,
60 .mask = 0x00000007,
68 .mask = 0x00000001,
811 .mask = PMX_MII_MASK,
1211 .mask = PMX_SSP_MASK,
1227 .mask = PMX_MII_MASK,
1420 .mask = PMX_SSP_MASK,
1436 .mask = PMX_MII_MASK,
[all …]
/drivers/infiniband/sw/rxe/
A Drxe_opcode.c17 .mask = {
24 .mask = {
31 .mask = {
40 .mask = {
49 .mask = {
55 .mask = {
61 .mask = {
67 .mask = {
73 .mask = {
81 .mask = {
[all …]

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