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Searched refs:mask2 (Results 1 – 25 of 37) sorted by relevance

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/drivers/ras/amd/atl/
A Dsystem.c67 static void df3p5_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) in df3p5_get_masks_shifts() argument
75 df_cfg.socket_id_mask = FIELD_GET(DF4_SOCKET_ID_MASK, mask2); in df3p5_get_masks_shifts()
76 df_cfg.die_id_mask = FIELD_GET(DF4_DIE_ID_MASK, mask2); in df3p5_get_masks_shifts()
79 static void df4_get_masks_shifts(u32 mask0, u32 mask1, u32 mask2) in df4_get_masks_shifts() argument
81 df3p5_get_masks_shifts(mask0, mask1, mask2); in df4_get_masks_shifts()
96 u32 mask0, mask1, mask2; in df4_get_fabric_id_mask_registers() local
107 if (df_indirect_read_broadcast(0, 4, 0x1B8, &mask2)) in df4_get_fabric_id_mask_registers()
110 df4_get_masks_shifts(mask0, mask1, mask2); in df4_get_fabric_id_mask_registers()
/drivers/soc/fsl/qe/
A Dgpio.c246 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2); in qe_pin_set_dedicated() local
253 qe_clrsetbits_be32(&regs->cpdir2, mask2, in qe_pin_set_dedicated()
254 sregs->cpdir2 & mask2); in qe_pin_set_dedicated()
255 qe_clrsetbits_be32(&regs->cppar2, mask2, in qe_pin_set_dedicated()
256 sregs->cppar2 & mask2); in qe_pin_set_dedicated()
258 qe_clrsetbits_be32(&regs->cpdir1, mask2, in qe_pin_set_dedicated()
259 sregs->cpdir1 & mask2); in qe_pin_set_dedicated()
260 qe_clrsetbits_be32(&regs->cppar1, mask2, in qe_pin_set_dedicated()
261 sregs->cppar1 & mask2); in qe_pin_set_dedicated()
/drivers/gpu/drm/amd/display/dc/
A Ddc_helper.c287 uint8_t shift2, uint32_t mask2, uint32_t *field_value2) in generic_reg_get2() argument
291 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get2()
297 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get3() argument
302 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get3()
309 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get4() argument
315 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get4()
323 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get5() argument
330 *field_value2 = get_reg_field_value_ex(reg_val, mask2, shift2); in generic_reg_get5()
339 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get6() argument
357 uint8_t shift2, uint32_t mask2, uint32_t *field_value2, in generic_reg_get7() argument
[all …]
/drivers/net/wireless/ath/ath9k/
A Dar9002_mac.c36 u32 mask2 = 0; in ar9002_hw_get_isr() local
67 mask2 |= ATH9K_INT_TIM; in ar9002_hw_get_isr()
69 mask2 |= ATH9K_INT_DTIM; in ar9002_hw_get_isr()
71 mask2 |= ATH9K_INT_DTIMSYNC; in ar9002_hw_get_isr()
73 mask2 |= ATH9K_INT_CABEND; in ar9002_hw_get_isr()
75 mask2 |= ATH9K_INT_GTT; in ar9002_hw_get_isr()
77 mask2 |= ATH9K_INT_CST; in ar9002_hw_get_isr()
79 mask2 |= ATH9K_INT_TSFOOR; in ar9002_hw_get_isr()
134 *masked |= mask2; in ar9002_hw_get_isr()
A Dar9003_mac.c187 u32 mask2 = 0; in ar9003_hw_get_isr() local
217 mask2 |= ((isr2 & AR_ISR_S2_TIM) >> in ar9003_hw_get_isr()
219 mask2 |= ((isr2 & AR_ISR_S2_DTIM) >> in ar9003_hw_get_isr()
221 mask2 |= ((isr2 & AR_ISR_S2_DTIMSYNC) >> in ar9003_hw_get_isr()
223 mask2 |= ((isr2 & AR_ISR_S2_CABEND) >> in ar9003_hw_get_isr()
225 mask2 |= ((isr2 & AR_ISR_S2_GTT) << in ar9003_hw_get_isr()
227 mask2 |= ((isr2 & AR_ISR_S2_CST) << in ar9003_hw_get_isr()
229 mask2 |= ((isr2 & AR_ISR_S2_TSFOOR) >> in ar9003_hw_get_isr()
231 mask2 |= ((isr2 & AR_ISR_S2_BB_WATCHDOG) >> in ar9003_hw_get_isr()
303 *masked |= mask2; in ar9003_hw_get_isr()
A Dmac.c911 u32 mask, mask2; in ath9k_hw_set_interrupts() local
928 mask2 = 0; in ath9k_hw_set_interrupts()
972 mask2 |= AR_IMR_S2_TIM; in ath9k_hw_set_interrupts()
974 mask2 |= AR_IMR_S2_DTIM; in ath9k_hw_set_interrupts()
976 mask2 |= AR_IMR_S2_DTIMSYNC; in ath9k_hw_set_interrupts()
978 mask2 |= AR_IMR_S2_CABEND; in ath9k_hw_set_interrupts()
980 mask2 |= AR_IMR_S2_TSFOOR; in ath9k_hw_set_interrupts()
986 mask2 |= AR_IMR_S2_GTT; in ath9k_hw_set_interrupts()
988 mask2 |= AR_IMR_S2_CST; in ath9k_hw_set_interrupts()
994 mask2 |= AR_IMR_S2_BB_WATCHDOG; in ath9k_hw_set_interrupts()
[all …]
/drivers/gpu/drm/amd/display/dc/irq/dcn21/
A Dirq_service_dcn21.c186 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
196 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
200 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
210 reg2 ## __ ## mask2 ## _MASK,\
212 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn31/
A Dirq_service_dcn31.c181 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
191 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
193 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
195 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
205 reg2 ## __ ## mask2 ## _MASK,\
207 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn314/
A Dirq_service_dcn314.c183 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
193 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
195 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
197 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
207 reg2 ## __ ## mask2 ## _MASK,\
209 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn315/
A Dirq_service_dcn315.c188 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
198 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
200 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
202 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
212 reg2 ## __ ## mask2 ## _MASK,\
214 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn30/
A Dirq_service_dcn30.c193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
207 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
217 reg2 ## __ ## mask2 ## _MASK,\
219 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn302/
A Dirq_service_dcn302.c178 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
186 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
187 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
196 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
206 reg2 ## __ ## mask2 ## _MASK,\
208 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn351/
A Dirq_service_dcn351.c159 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
169 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
171 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
173 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
183 reg2 ## __ ## mask2 ## _MASK,\
185 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn401/
A Dirq_service_dcn401.c172 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
182 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
184 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
186 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
196 reg2 ## __ ## mask2 ## _MASK,\
198 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn32/
A Dirq_service_dcn32.c192 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
202 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
204 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
206 #define IRQ_REG_ENTRY_DMUB(reg1, mask1, reg2, mask2)\ argument
216 reg2 ## __ ## mask2 ## _MASK,\
218 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn35/
A Dirq_service_dcn35.c180 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
190 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
192 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
194 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
204 reg2 ## __ ## mask2 ## _MASK,\
206 reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn36/
A Dirq_service_dcn36.c158 #define IRQ_REG_ENTRY(base, block, reg_num, reg1, mask1, reg2, mask2)\ argument
168 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
170 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
172 #define IRQ_REG_ENTRY_DMUB(base, reg1, mask1, reg2, mask2)\ argument
182 reg2 ## __ ## mask2 ## _MASK,\
184 reg2 ## __ ## mask2 ## _MASK \
/drivers/net/hamradio/
A Dbaycom_par.c206 unsigned int data, mask, mask2, descx; in par96_rx() local
235 for(mask = 0x1fe00, mask2 = 0xfc00, i = 0; in par96_rx()
236 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) in par96_rx()
237 if ((bc->modem.par96.dcd_shreg & mask) == mask2) in par96_rx()
240 for(mask = 0x1fe00, mask2 = 0x1fe00, i = 0; in par96_rx()
241 i < PAR96_BURSTBITS; i++, mask <<= 1, mask2 <<= 1) in par96_rx()
242 if (((bc->modem.par96.dcd_shreg & mask) == mask2) && in par96_rx()
A Dhdlcdrv.c159 unsigned int mask1, mask2, mask3, mask4, mask5, mask6, word; in hdlcdrv_receiver() local
177 for(i = 15, mask1 = 0x1fc00, mask2 = 0x1fe00, mask3 = 0x0fc00, in hdlcdrv_receiver()
180 i--, mask1 <<= 1, mask2 <<= 1, mask3 <<= 1, mask4 <<= 1, in hdlcdrv_receiver()
184 else if ((s->hdlcrx.bitstream & mask2) == mask3) { in hdlcdrv_receiver()
255 unsigned int mask1, mask2, mask3; in hdlcdrv_transmitter() local
331 mask2 = 0x10000; in hdlcdrv_transmitter()
334 for(i = 0; i < 8; i++, mask1 <<= 1, mask2 <<= 1, in hdlcdrv_transmitter()
338 s->hdlctx.bitstream &= ~mask2; in hdlcdrv_transmitter()
/drivers/media/test-drivers/vidtv/
A Dvidtv_pes.c90 u64 mask2; in vidtv_pes_write_pts_dts() local
97 mask2 = GENMASK_ULL(29, 15); in vidtv_pes_write_pts_dts()
103 pts_dts.pts2 = cpu_to_be16(((args->pts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()
107 pts_dts.dts2 = cpu_to_be16(((args->dts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()
115 pts.pts2 = cpu_to_be16(((args->pts & mask2) >> 14) | 0x1); in vidtv_pes_write_pts_dts()
/drivers/power/supply/
A Drt9455_charger.c855 unsigned int irq1, mask1, mask2; in rt9455_irq_handler_check_irq1_register() local
897 ret = regmap_read(info->regmap, RT9455_REG_MASK2, &mask2); in rt9455_irq_handler_check_irq1_register()
903 if (mask2 & GET_MASK(F_CHTERMIM)) { in rt9455_irq_handler_check_irq1_register()
912 if (mask2 & GET_MASK(F_CHRCHGIM)) { in rt9455_irq_handler_check_irq1_register()
949 unsigned int irq2, mask2; in rt9455_irq_handler_check_irq2_register() local
960 ret = regmap_read(info->regmap, RT9455_REG_MASK2, &mask2); in rt9455_irq_handler_check_irq2_register()
990 if ((mask2 & GET_MASK(F_CHTERMIM)) == 0) { in rt9455_irq_handler_check_irq2_register()
1001 mask2 = mask2 | GET_MASK(F_CHTERMIM); in rt9455_irq_handler_check_irq2_register()
1015 if (mask2 & GET_MASK(F_CHTERMIM)) { in rt9455_irq_handler_check_irq2_register()
1023 mask2 = mask2 & ~GET_MASK(F_CHTERMIM); in rt9455_irq_handler_check_irq2_register()
/drivers/gpu/drm/amd/display/dc/irq/dce120/
A Dirq_service_dce120.c76 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
86 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
88 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn303/
A Dirq_service_dcn303.c121 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
129 .ack_mask = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
130 .ack_value = block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn201/
A Dirq_service_dcn201.c125 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
135 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
137 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
/drivers/gpu/drm/amd/display/dc/irq/dcn10/
A Dirq_service_dcn10.c173 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
183 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
185 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \

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