Searched refs:mask_addr (Results 1 – 9 of 9) sorted by relevance
| /drivers/ata/ |
| A D | sata_vsc.c | 106 void __iomem *mask_addr; in vsc_freeze() local
108 mask_addr = ap->host->iomap[VSC_MMIO_BAR] + in vsc_freeze()
111 writeb(0, mask_addr); in vsc_freeze()
117 void __iomem *mask_addr; in vsc_thaw() local
119 mask_addr = ap->host->iomap[VSC_MMIO_BAR] + in vsc_thaw()
122 writeb(0xff, mask_addr); in vsc_thaw()
128 void __iomem *mask_addr; in vsc_intr_mask_update() local
131 mask_addr = ap->host->iomap[VSC_MMIO_BAR] + in vsc_intr_mask_update()
133 mask = readb(mask_addr); in vsc_intr_mask_update()
138 writeb(mask, mask_addr); in vsc_intr_mask_update()
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| /drivers/net/ethernet/ti/icssg/ |
| A D | icssg_classifier.c | 420 u8 mask_addr[6] = { 0, 0, 0, 0, 0, 0xff }; in icssg_class_add_mcast_sr1() local
431 eth_reserved_addr_base, mask_addr); in icssg_class_add_mcast_sr1()
433 eth_ipv4_mcast_addr_base, mask_addr); in icssg_class_add_mcast_sr1()
434 mask_addr[5] = 0; in icssg_class_add_mcast_sr1()
453 ha->addr, mask_addr); in icssg_class_add_mcast_sr1()
462 const u8 mask_addr[] = { 0, 0, 0, 0, 0, 0, }; in icssg_ft1_set_mac_addr() local
466 rx_class_ft1_set_da_mask(miig_rt, slice, 0, mask_addr); in icssg_ft1_set_mac_addr()
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| /drivers/video/fbdev/ |
| A D | hitfb.c | 92 u32 mask_addr) in hitfb_accel_bitblt() argument
103 if (mask_addr) { in hitfb_accel_bitblt()
116 if (mask_addr) { in hitfb_accel_bitblt()
132 if (mask_addr) { in hitfb_accel_bitblt()
133 maddr += mask_addr; in hitfb_accel_bitblt()
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| /drivers/net/ethernet/broadcom/bnx2x/ |
| A D | bnx2x_init.h | 561 u32 mask_addr; member
712 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr, in bnx2x_disable_blocks_parity()
777 REG_WR(bp, bnx2x_blocks_parity_data[i].mask_addr, in bnx2x_enable_blocks_parity()
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| /drivers/dma/stm32/ |
| A D | stm32-mdma.c | 199 u32 mask_addr; member
709 hwdesc->cmar = config->mask_addr; in stm32_mdma_setup_hwdesc()
1310 chan->chan_config.mask_addr = mdma_config->cmar; in stm32_mdma_slave_config()
1559 config.mask_addr = dma_spec->args[3]; in stm32_mdma_of_xlate()
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| /drivers/net/ethernet/hisilicon/hns3/ |
| A D | hns3_debugfs.c | 419 reg_val = readl(tqp_vector->mask_addr + gl_offset) & in hns3_get_coal_info()
423 reg_val = readl(tqp_vector->mask_addr + ql_offset) & in hns3_get_coal_info()
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| A D | hns3_enet.h | 555 u8 __iomem *mask_addr; member
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| A D | hns3_enet.c | 474 writel(mask_en, tqp_vector->mask_addr); in hns3_mask_vector_irq()
507 writel(rl_reg, tqp_vector->mask_addr + HNS3_VECTOR_RL_OFFSET); in hns3_set_vector_coalesce_rl()
520 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL0_OFFSET); in hns3_set_vector_coalesce_rx_gl()
533 writel(new_val, tqp_vector->mask_addr + HNS3_VECTOR_GL1_OFFSET); in hns3_set_vector_coalesce_tx_gl()
539 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_TX_QL_OFFSET); in hns3_set_vector_coalesce_tx_ql()
545 writel(ql_value, tqp_vector->mask_addr + HNS3_VECTOR_RX_QL_OFFSET); in hns3_set_vector_coalesce_rx_ql()
2841 readl(tx_ring->tqp_vector->mask_addr)); in hns3_dump_queue_reg()
4815 tqp_vector->mask_addr = vector[i].io_addr; in hns3_nic_alloc_vector_data()
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| /drivers/net/ethernet/intel/ice/ |
| A D | ice_dpll.c | 2763 u16 mask_addr = addr + ICE_DPLL_PFA_MASK_OFFSET; in ice_dpll_init_ref_sync_inputs() local
2766 ret = ice_read_sr_word(hw, mask_addr, &mask); in ice_dpll_init_ref_sync_inputs()
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