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Searched refs:mask_offset (Results 1 – 3 of 3) sorted by relevance

/drivers/perf/hisilicon/
A Dhisi_uncore_pa_pmu.c56 u32 mask_offset; member
238 val = readl(pa_pmu->base + regs->mask_offset); in hisi_pa_pmu_enable_counter_int()
240 writel(val, pa_pmu->base + regs->mask_offset); in hisi_pa_pmu_enable_counter_int()
250 val = readl(pa_pmu->base + regs->mask_offset); in hisi_pa_pmu_disable_counter_int()
252 writel(val, pa_pmu->base + regs->mask_offset); in hisi_pa_pmu_disable_counter_int()
357 .mask_offset = PA_INT_MASK,
391 .mask_offset = H60PA_INT_MASK,
/drivers/pci/controller/plda/
A Dpcie-microchip-host.c137 .mask_offset = PCIE_EVENT_INT, \
144 .mask_offset = SEC_ERROR_INT_MASK, \
151 .mask_offset = DED_ERROR_INT_MASK, \
158 .mask_offset = IMASK_LOCAL, \
263 u32 mask_offset; member
438 addr += event_descs[event].mask_offset; in mc_mask_event_irq()
473 addr += event_descs[event].mask_offset; in mc_unmask_event_irq()
/drivers/irqchip/
A Dirq-brcmstb-l2.c59 int mask_offset; member
74 ~(irq_reg_readl(b->gc, b->mask_offset)); in brcmstb_l2_intc_irq_handle()
214 data->mask_offset = init_params->cpu_mask_status; in brcmstb_l2_intc_of_init()

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