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Searched refs:max_bpp_x16 (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/i915/display/
A Dintel_link_bw.c75 limits->max_bpp_x16[pipe] = min(limits->max_bpp_x16[pipe], forced_bpp_x16); in intel_link_bw_init_limits()
108 int max_bpp_x16 = 0; in __intel_link_bw_reduce_bpp() local
137 if (link_bpp_x16 > max_bpp_x16) { in __intel_link_bw_reduce_bpp()
138 max_bpp_x16 = link_bpp_x16; in __intel_link_bw_reduce_bpp()
146 limits->max_bpp_x16[max_bpp_pipe] = max_bpp_x16 - 1; in __intel_link_bw_reduce_bpp()
197 old_limits->max_bpp_x16[pipe]) in intel_link_bw_set_bpp_limit_for_pipe()
204 new_limits->max_bpp_x16[pipe] = in intel_link_bw_set_bpp_limit_for_pipe()
205 old_limits->max_bpp_x16[pipe]; in intel_link_bw_set_bpp_limit_for_pipe()
249 new_limits->max_bpp_x16[pipe] > in assert_link_limit_change_valid()
250 old_limits->max_bpp_x16[pipe])) in assert_link_limit_change_valid()
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A Dintel_dp_mst.c260 int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc) in intel_dp_mtp_tu_compute_config() argument
276 fxp_q4_to_frac(max_bpp_x16) || in intel_dp_mtp_tu_compute_config()
281 drm_WARN_ON(display->drm, min_bpp_x16 != max_bpp_x16); in intel_dp_mtp_tu_compute_config()
304 if (max_dpt_bpp_x16 && max_bpp_x16 > max_dpt_bpp_x16) { in intel_dp_mtp_tu_compute_config()
306 FXP_Q4_ARGS(max_bpp_x16), FXP_Q4_ARGS(max_dpt_bpp_x16)); in intel_dp_mtp_tu_compute_config()
307 max_bpp_x16 = max_dpt_bpp_x16; in intel_dp_mtp_tu_compute_config()
311 FXP_Q4_ARGS(min_bpp_x16), FXP_Q4_ARGS(max_bpp_x16)); in intel_dp_mtp_tu_compute_config()
455 limits->link.max_bpp_x16, in mst_stream_compute_link_config()
496 max_compressed_bpp_x16 = limits->link.max_bpp_x16; in mst_stream_dsc_compute_link_config()
580 if (limits->link.max_bpp_x16 < fxp_q4_from_int(24)) in adjust_limits_for_dsc_hblank_expansion_quirk()
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A Dintel_link_bw.h21 int max_bpp_x16[I915_MAX_PIPES]; member
A Dintel_dp_mst.h37 int min_bpp_x16, int max_bpp_x16, int bpp_step_x16, bool dsc);
A Dintel_dp.h35 int min_bpp_x16, max_bpp_x16; member
A Dintel_dp.c1778 for (bpp = fxp_q4_to_int(limits->link.max_bpp_x16); in intel_dp_compute_link_config_wide()
2168 int min_bpp_x16, max_bpp_x16, bpp_step_x16; in dsc_compute_compressed_bpp() local
2177 max_bpp_x16 = min(fxp_q4_from_int(dsc_joiner_max_bpp), limits->link.max_bpp_x16); in dsc_compute_compressed_bpp()
2183 max_bpp_x16 = min(max_bpp_x16, fxp_q4_from_int(output_bpp) - bpp_step_x16); in dsc_compute_compressed_bpp()
2187 max_bpp_x16 = round_down(max_bpp_x16, bpp_step_x16); in dsc_compute_compressed_bpp()
2189 for (bpp_x16 = max_bpp_x16; bpp_x16 >= min_bpp_x16; bpp_x16 -= bpp_step_x16) { in dsc_compute_compressed_bpp()
2328 dsc_max_bpp = fxp_q4_to_int(limits->link.max_bpp_x16); in intel_edp_dsc_compute_pipe_bpp()
2508 limits->link.max_bpp_x16 = max_link_bpp_x16; in intel_dp_compute_config_link_bpp_limits()
2519 FXP_Q4_ARGS(limits->link.max_bpp_x16)); in intel_dp_compute_config_link_bpp_limits()
A Dintel_display.c4637 crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe]; in intel_modeset_pipe_config()
/drivers/gpu/drm/amd/display/dc/dsc/
A Ddc_dsc.c162 const uint32_t max_bpp_x16,
462 uint32_t max_bpp_x16, in dc_dsc_compute_bandwidth_range() argument
476 options.max_target_bpp_limit_override_x16 = max_bpp_x16; in dc_dsc_compute_bandwidth_range()
491 is_dsc_possible = decide_dsc_bandwidth_range(min_bpp_x16, max_bpp_x16, in dc_dsc_compute_bandwidth_range()
799 const uint32_t max_bpp_x16, in decide_dsc_bandwidth_range() argument
812 if (preferred_bpp_x16 <= max_bpp_x16 && in decide_dsc_bandwidth_range()
822 max_bpp_x16); in decide_dsc_bandwidth_range()
826 range->max_target_bpp_x16 = max_bpp_x16; in decide_dsc_bandwidth_range()
/drivers/gpu/drm/amd/display/dc/
A Ddc_dsc.h74 uint32_t max_bpp_x16,

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