Home
last modified time | relevance | path

Searched refs:max_clk (Results 1 – 23 of 23) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_cfg.c103 .max_clk = 200000000,
184 .max_clk = 200000000,
271 .max_clk = 320000000,
371 .max_clk = 320000000,
443 .max_clk = 320000000,
523 .max_clk = 366670000,
623 .max_clk = 400000000,
736 .max_clk = 412500000,
833 .max_clk = 360000000,
925 .max_clk = 400000000,
[all …]
A Dmdp5_cfg.h115 uint32_t max_clk; member
A Dmdp5_kms.c742 clk_set_rate(mdp5_kms->core_clk, config->hw->max_clk); in mdp5_init()
/drivers/mmc/host/
A Dsdhci-of-esdhc.c36 const unsigned int max_clk[MMC_TIMING_NUM]; member
41 .max_clk[MMC_TIMING_MMC_HS] = 46500000,
42 .max_clk[MMC_TIMING_SD_HS] = 46500000,
47 .max_clk[MMC_TIMING_UHS_SDR104] = 116700000,
48 .max_clk[MMC_TIMING_MMC_HS200] = 116700000,
53 .max_clk[MMC_TIMING_UHS_SDR104] = 167000000,
54 .max_clk[MMC_TIMING_MMC_HS200] = 167000000,
60 .max_clk[MMC_TIMING_MMC_HS200] = 125000000,
65 .max_clk[MMC_TIMING_LEGACY] = 20000000,
66 .max_clk[MMC_TIMING_MMC_HS] = 42000000,
[all …]
A Dbcm2835.c156 unsigned int max_clk; /* Max possible freq */ member
1129 div = host->max_clk / clock; in bcm2835_set_clock()
1132 if ((host->max_clk / div) > clock) in bcm2835_set_clock()
1139 clock = host->max_clk / (div + 2); in bcm2835_set_clock()
1266 if (!mmc->f_max || mmc->f_max > host->max_clk) in bcm2835_add_host()
1267 mmc->f_max = host->max_clk; in bcm2835_add_host()
1268 mmc->f_min = host->max_clk / SDCDIV_MAX_CDIV; in bcm2835_add_host()
1436 host->max_clk = clk_get_rate(host->clk); in bcm2835_probe()
A Dsdhci.c1972 if (host->max_clk <= clock) in sdhci_calc_clk()
1977 if ((host->max_clk / div) <= clock) in sdhci_calc_clk()
1984 && !div && host->max_clk <= 25000000) in sdhci_calc_clk()
1990 if ((host->max_clk / div) <= clock) in sdhci_calc_clk()
4272 u32 max_clk; in sdhci_setup_host() local
4429 host->max_clk *= 1000000; in sdhci_setup_host()
4430 if (host->max_clk == 0 || host->quirks & in sdhci_setup_host()
4459 max_clk = host->max_clk; in sdhci_setup_host()
4465 max_clk = host->max_clk * host->clk_mul; in sdhci_setup_host()
4474 if (!mmc->f_max || mmc->f_max > max_clk) in sdhci_setup_host()
[all …]
A Dsdhci-of-aspeed.c254 if (WARN_ON(clock > host->max_clk)) in aspeed_sdhci_set_clock()
255 clock = host->max_clk; in aspeed_sdhci_set_clock()
A Dsdhci-cadence.c199 return host->max_clk; in sdhci_cdns_get_timeout_clock()
A Dsdhci-s3c.c264 host->max_clk = ourhost->clk_rates[best_src]; in sdhci_s3c_set_clock()
A Dsdhci.h578 unsigned int max_clk; /* Max possible freq (MHz) */ member
A Dsdhci-tegra.c780 host->max_clk = host_clk; in tegra_sdhci_set_clock()
782 host->max_clk = clk_get_rate(pltfm_host->clk); in tegra_sdhci_set_clock()
A Dsdhci-of-arasan.c371 sdhci_set_clock(host, host->max_clk); in sdhci_arasan_set_clock()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Daldebaran_ppt.c351 uint32_t min_clk, max_clk; in aldebaran_get_dpm_ultimate_freq() local
380 max_clk = dpm_table->max; in aldebaran_get_dpm_ultimate_freq()
388 if (!max_clk) in aldebaran_get_dpm_ultimate_freq()
390 *max = max_clk; in aldebaran_get_dpm_ultimate_freq()
838 uint32_t min_clk, max_clk, cur_value = 0; in aldebaran_emit_clk_levels() local
871 max_clk = pstate_table->gfxclk_pstate.curr.max; in aldebaran_emit_clk_levels()
874 freq_values[1] = max_clk; in aldebaran_emit_clk_levels()
879 freq_values[2] = max_clk; in aldebaran_emit_clk_levels()
1370 uint32_t max_clk; in aldebaran_set_soft_freq_limited_range() local
1438 uint32_t max_clk; in aldebaran_usr_edit_dpm_table() local
[all …]
A Dsmu_v13_0_6_ppt.c889 uint32_t min_clk, max_clk, param; in smu_v13_0_6_get_dpm_ultimate_freq() local
920 max_clk = dpm_table->max; in smu_v13_0_6_get_dpm_ultimate_freq()
925 *max = max_clk; in smu_v13_0_6_get_dpm_ultimate_freq()
927 if (min_clk && max_clk) in smu_v13_0_6_get_dpm_ultimate_freq()
1363 uint32_t min_clk, max_clk; in smu_v13_0_6_print_clk_levels() local
1400 max_clk); in smu_v13_0_6_print_clk_levels()
1409 max_clk); in smu_v13_0_6_print_clk_levels()
1415 max_clk, in smu_v13_0_6_print_clk_levels()
2023 uint32_t max_clk; in smu_v13_0_6_set_soft_freq_limited_range() local
2085 max_clk); in smu_v13_0_6_set_soft_freq_limited_range()
[all …]
A Dsmu_v13_0_5_ppt.c823 uint32_t max_clk = max; in smu_v13_0_5_set_soft_freq_limited_range() local
846 max_clk = max << SMU_13_VCLK_SHIFT; in smu_v13_0_5_set_soft_freq_limited_range()
853 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL); in smu_v13_0_5_set_soft_freq_limited_range()
973 uint32_t *max_clk) in smu_v13_0_5_get_dpm_profile_freq() argument
997 *min_clk = *max_clk = clk_limit; in smu_v13_0_5_get_dpm_profile_freq()
A Dsmu_v13_0_4_ppt.c844 uint32_t max_clk = max; in smu_v13_0_4_set_soft_freq_limited_range() local
875 max_clk = max << SMU_13_VCLK_SHIFT; in smu_v13_0_4_set_soft_freq_limited_range()
883 max_clk, NULL); in smu_v13_0_4_set_soft_freq_limited_range()
924 uint32_t *max_clk) in smu_v13_0_4_get_dpm_profile_freq() argument
960 *min_clk = *max_clk = clk_limit; in smu_v13_0_4_get_dpm_profile_freq()
A Dyellow_carp_ppt.c957 uint32_t max_clk = max; in yellow_carp_set_soft_freq_limited_range() local
989 max_clk = max << SMU_13_VCLK_SHIFT; in yellow_carp_set_soft_freq_limited_range()
997 ret = smu_cmn_send_smc_msg_with_param(smu, msg_set_max, max_clk, NULL); in yellow_carp_set_soft_freq_limited_range()
1157 uint32_t *max_clk) in yellow_carp_get_dpm_profile_freq() argument
1192 *min_clk = *max_clk = clk_limit; in yellow_carp_get_dpm_profile_freq()
/drivers/gpu/drm/msm/disp/mdp4/
A Dmdp4_kms.c402 unsigned long max_clk; in mdp4_kms_init() local
405 max_clk = 266667000; in mdp4_kms_init()
425 clk_set_rate(mdp4_kms->clk, max_clk); in mdp4_kms_init()
444 clk_set_rate(mdp4_kms->lut_clk, max_clk); in mdp4_kms_init()
/drivers/gpu/drm/bridge/
A Dsil-sii8620.c1176 int max_clk; in sii8620_start_video() member
1193 if (clk < clk_spec[i].max_clk) in sii8620_start_video()
1196 if (100 * clk >= 98 * clk_spec[i].max_clk) in sii8620_start_video()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0_0_ppt.c1304 uint32_t *max_clk) in smu_v14_0_common_get_dpm_profile_freq() argument
1355 *min_clk = *max_clk = clk_limit; in smu_v14_0_common_get_dpm_profile_freq()
/drivers/accel/habanalabs/common/
A Dfirmware_if.c3132 int hl_fw_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk) in hl_fw_get_clk_rate() argument
3141 *max_clk = 0; in hl_fw_get_clk_rate()
3152 *max_clk = (value / 1000 / 1000); in hl_fw_get_clk_rate()
A Dhabanalabs.h4029 int hl_fw_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
/drivers/net/ethernet/mediatek/
A Dmtk_eth_soc.c977 unsigned int max_clk = 2500000; in mtk_mdio_init() local
1010 max_clk = val; in mtk_mdio_init()
1012 eth->mdc_divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); in mtk_mdio_init()

Completed in 99 milliseconds