Searched refs:max_handles (Results 1 – 14 of 14) sorted by relevance
| /drivers/gpu/drm/radeon/ |
| A D | radeon_uvd.c | 138 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()
168 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES; in radeon_uvd_init()
188 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles; in radeon_uvd_init()
221 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_init()
258 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_suspend()
332 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_free_handles()
507 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()
533 for (i = 0; i < p->rdev->uvd.max_handles; ++i) { in radeon_uvd_cs_msg()
548 for (i = 0; i < p->rdev->uvd.max_handles; ++i) in radeon_uvd_cs_msg()
848 for (i = 0; i < rdev->uvd.max_handles; ++i) { in radeon_uvd_count_handles()
|
| A D | uvd_v4_2.c | 62 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v4_2_resume()
75 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles); in uvd_v4_2_resume()
|
| A D | uvd_v2_2.c | 125 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v2_2_resume()
|
| A D | uvd_v1_0.c | 133 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v1_0_resume()
|
| A D | radeon.h | 1667 unsigned max_handles; member
|
| /drivers/gpu/drm/amd/amdgpu/ |
| A D | amdgpu_uvd.c | 272 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; in amdgpu_uvd_sw_init()
293 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; in amdgpu_uvd_sw_init()
312 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; in amdgpu_uvd_sw_init()
337 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_sw_init()
432 for (i = 0; i < adev->uvd.max_handles; ++i) in amdgpu_uvd_prepare_suspend()
436 if (i == adev->uvd.max_handles) in amdgpu_uvd_prepare_suspend()
525 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_free_handles()
853 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_cs_msg()
877 for (i = 0; i < adev->uvd.max_handles; ++i) { in amdgpu_uvd_cs_msg()
892 for (i = 0; i < adev->uvd.max_handles; ++i) in amdgpu_uvd_cs_msg()
[all …]
|
| A D | amdgpu_uvd.h | 57 unsigned max_handles; member
|
| A D | uvd_v3_1.c | 258 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; in uvd_v3_1_mc_resume()
|
| A D | uvd_v4_2.c | 592 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; in uvd_v4_2_mc_resume()
|
| A D | uvd_v6_0.c | 627 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); in uvd_v6_0_mc_resume()
635 WREG32(mmUVD_GP_SCRATCH4, adev->uvd.max_handles); in uvd_v6_0_mc_resume()
|
| A D | uvd_v5_0.c | 303 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); in uvd_v5_0_mc_resume()
|
| A D | uvd_v7_0.c | 726 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles); in uvd_v7_0_mc_resume()
862 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles); in uvd_v7_0_sriov_start()
|
| A D | amdgpu_kms.c | 1110 handle.uvd_max_handles = adev->uvd.max_handles; in amdgpu_info_ioctl()
|
| /drivers/cxl/core/ |
| A D | mbox.c | 990 u8 max_handles = CXL_CLEAR_EVENT_MAX_HANDLES; in cxl_clear_event_record() local
991 size_t pl_size = struct_size(payload, handles, max_handles); in cxl_clear_event_record()
999 max_handles = (cxl_mbox->payload_size - sizeof(*payload)) / in cxl_clear_event_record()
1001 pl_size = struct_size(payload, handles, max_handles); in cxl_clear_event_record()
1031 if (i == max_handles) { in cxl_clear_event_record()
|
Completed in 48 milliseconds