Searched refs:max_pfn (Results 1 – 25 of 37) sorted by relevance
12
303 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()306 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_0_setup_vmid_config()
323 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()326 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_0_setup_vmid_config()
335 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_3_setup_vmid_config()338 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_3_setup_vmid_config()
169 #define AMDGPU_VA_RESERVED_CSA_START(adev) (((adev)->vm_manager.max_pfn \442 uint64_t max_pfn; member
333 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v11_5_0_setup_vmid_config()336 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v11_5_0_setup_vmid_config()
338 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v12_0_setup_vmid_config()341 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v12_0_setup_vmid_config()
330 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()333 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v3_0_setup_vmid_config()
352 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()355 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_2_setup_vmid_config()
354 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_1_setup_vmid_config()357 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_1_setup_vmid_config()
404 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()407 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_0_setup_vmid_config()
322 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()325 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v2_3_setup_vmid_config()
360 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_setup_vmid_config()363 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_0_setup_vmid_config()
448 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_3_setup_vmid_config()451 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v3_3_setup_vmid_config()
353 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v4_1_0_setup_vmid_config()356 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v4_1_0_setup_vmid_config()
335 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()338 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v2_1_setup_vmid_config()
391 lower_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_2_xcc_setup_vmid_config()395 upper_32_bits(adev->vm_manager.max_pfn - 1)); in gfxhub_v1_2_xcc_setup_vmid_config()
126 queue_input.process_va_end = adev->vm_manager.max_pfn - 1; in mes_userq_map()
327 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()330 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_0_setup_vmid_config()
435 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_8_setup_vmid_config()439 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_8_setup_vmid_config()
446 uint32_t high = adev->vm_manager.max_pfn - in gmc_v6_0_set_prt()527 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v6_0_gart_enable()
576 uint32_t high = adev->vm_manager.max_pfn - in gmc_v7_0_set_prt()674 WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1); in gmc_v7_0_gart_enable()
337 lower_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_7_setup_vmid_config()340 upper_32_bits(adev->vm_manager.max_pfn - 1)); in mmhub_v1_7_setup_vmid_config()
82 return round_up(adev->vm_manager.max_pfn, 1ULL << shift) in amdgpu_vm_pt_num_entries()
62 return rdev->vm_manager.max_pfn >> radeon_vm_block_size; in radeon_vm_num_pdes()465 if (last_pfn >= rdev->vm_manager.max_pfn) { in radeon_vm_bo_set_addr()467 last_pfn, rdev->vm_manager.max_pfn); in radeon_vm_bo_set_addr()
700 extra_pfn_end = min(max_pfn, start_pfn + pages); in balloon_add_regions()
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