Searched refs:max_tile_pipes (Results 1 – 21 of 21) sorted by relevance
372 *value = rdev->config.cik.max_tile_pipes; in radeon_info_ioctl()374 *value = rdev->config.si.max_tile_pipes; in radeon_info_ioctl()376 *value = rdev->config.cayman.max_tile_pipes; in radeon_info_ioctl()378 *value = rdev->config.evergreen.max_tile_pipes; in radeon_info_ioctl()380 *value = rdev->config.rv770.max_tile_pipes; in radeon_info_ioctl()382 *value = rdev->config.r600.max_tile_pipes; in radeon_info_ioctl()
1195 rdev->config.rv770.max_tile_pipes = 8; in rv770_gpu_init()1215 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1239 rdev->config.rv770.max_tile_pipes = 2; in rv770_gpu_init()1259 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1321 switch (rdev->config.rv770.max_tile_pipes) { in rv770_gpu_init()1336 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; in rv770_gpu_init()
3158 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3180 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3202 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3225 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3247 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3269 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3297 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3319 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3341 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3363 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()[all …]
2007 unsigned max_tile_pipes; member2029 unsigned max_tile_pipes; member2056 unsigned max_tile_pipes; member2083 unsigned max_tile_pipes; member2121 unsigned max_tile_pipes; member2152 unsigned max_tile_pipes; member
2008 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()2024 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()2042 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()2057 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()2088 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()2104 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
3081 rdev->config.si.max_tile_pipes = 12; in si_gpu_init()3098 rdev->config.si.max_tile_pipes = 8; in si_gpu_init()3116 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3133 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3150 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3187 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; in si_gpu_init()
882 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()906 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
2346 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()3179 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3196 rdev->config.cik.max_tile_pipes = 16; in cik_gpu_init()3213 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3232 rdev->config.cik.max_tile_pipes = 2; in cik_gpu_init()3267 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes; in cik_gpu_init()
1590 adev->gfx.config.max_tile_pipes = 12; in gfx_v6_0_constants_init()1607 adev->gfx.config.max_tile_pipes = 8; in gfx_v6_0_constants_init()1624 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1641 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1658 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1687 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v6_0_constants_init()
228 unsigned max_tile_pipes; member
4144 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()4161 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_early_init()4178 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()4197 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_early_init()4222 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
1650 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1667 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()1714 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()1731 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1748 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1765 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()1790 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
746 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; in amdgpu_atombios_get_gfx_info()
896 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
938 adev->gfx.config.max_tile_pipes = in gfx_v9_4_3_gpu_early_init()
3551 adev->gfx.config.max_tile_pipes = in get_gb_addr_config()
4689 adev->gfx.config.max_tile_pipes = in get_gb_addr_config()
2121 adev->gfx.config.max_tile_pipes = in gfx_v9_0_gpu_early_init()
4633 adev->gfx.config.max_tile_pipes = in gfx_v10_0_gpu_early_init()
1795 uint8_t max_tile_pipes; member1815 uint8_t max_tile_pipes; member1916 uint8_t max_tile_pipes; member
5653 UCHAR max_tile_pipes; member5666 UCHAR max_tile_pipes; member
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