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Searched refs:mci_writel (Results 1 – 9 of 9) sorted by relevance

/drivers/mmc/host/
A Ddw_mmc.c197 mci_writel(host, CTRL, ctrl); in dw_mci_ctrl_reset()
239 mci_writel(host, CMDARG, arg); in mci_send_cmd()
453 mci_writel(host, BMOD, bmod); in dw_mci_idmac_reset()
464 mci_writel(host, CTRL, temp); in dw_mci_idmac_stop_dma()
470 mci_writel(host, BMOD, temp); in dw_mci_idmac_stop_dma()
746 mci_writel(host, CTRL, temp); in dw_mci_idmac_start_dma()
754 mci_writel(host, BMOD, temp); in dw_mci_idmac_start_dma()
757 mci_writel(host, PLDMND, 1); in dw_mci_idmac_start_dma()
1119 mci_writel(host, CTRL, temp); in dw_mci_submit_data_dma()
1218 mci_writel(host, CLKENA, 0); in dw_mci_setup_bus()
[all …]
A Ddw_mmc-exynos.c115 mci_writel(host, MPSBEGIN0, 0); in dw_mci_exynos_config_smu()
177 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_set_clksel_timing()
179 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_set_clksel_timing()
259 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_resume_noirq()
261 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_resume_noirq()
299 mci_writel(host, HS400_DQS_EN, dqs); in dw_mci_exynos_config_hs400()
464 mci_writel(host, CLKSEL64, clksel); in dw_mci_exynos_set_clksmpl()
466 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_set_clksmpl()
494 mci_writel(host, CLKSEL, clksel); in dw_mci_exynos_move_next_clksmpl()
549 mci_writel(host, TMOUT, ~0); in dw_mci_exynos_execute_tuning()
[all …]
A Ddw_mmc-hi3798cv200.c37 mci_writel(host, UHS_REG, val); in dw_mci_hi3798cv200_set_ios()
44 mci_writel(host, ENABLE_SHIFT, val); in dw_mci_hi3798cv200_set_ios()
51 mci_writel(host, DDR_REG, val); in dw_mci_hi3798cv200_set_ios()
73 mci_writel(host, RINTSTS, ALL_INT_CLR); in dw_mci_hi3798cv200_execute_tuning()
116 mci_writel(host, RINTSTS, ALL_INT_CLR); in dw_mci_hi3798cv200_execute_tuning()
A Ddw_mmc-k3.c249 mci_writel(host, GPIO, 0x0); in dw_mci_hs_set_timing()
255 mci_writel(host, UHS_REG_EXT, reg_value); in dw_mci_hs_set_timing()
257 mci_writel(host, ENABLE_SHIFT, enable_shift); in dw_mci_hs_set_timing()
261 mci_writel(host, GPIO, (unsigned int)reg_value | GPIO_CLK_ENABLE); in dw_mci_hs_set_timing()
269 mci_writel(host, CDTHRCTL, SDMMC_SET_THLD(SDCARD_RD_THRESHOLD, in dw_mci_hi3660_init()
379 mci_writel(host, TMOUT, ~0); in dw_mci_hi3660_execute_tuning()
A Ddw_mmc-starfive.c50 mci_writel(host, UHS_REG_EXT, reg_value); in dw_mci_starfive_set_sample_phase()
66 mci_writel(host, RINTSTS, ALL_INT_CLR); in dw_mci_starfive_execute_tuning()
94 mci_writel(host, RINTSTS, ALL_INT_CLR); in dw_mci_starfive_execute_tuning()
A Ddw_mmc-hi3798mv200.c48 mci_writel(host, ENABLE_SHIFT, val); in dw_mci_hi3798mv200_set_ios()
55 mci_writel(host, DDR_REG, val); in dw_mci_hi3798mv200_set_ios()
110 mci_writel(host, RINTSTS, ALL_INT_CLR); in dw_mci_hi3798mv200_execute_tuning_mix_mode()
175 mci_writel(host, RINTSTS, ALL_INT_CLR); in dw_mci_hi3798mv200_execute_tuning_mix_mode()
A Ddw_mmc-bluefield.c38 mci_writel(host, UHS_REG_EXT, reg); in dw_mci_bluefield_set_ios()
A Ddw_mmc-rockchip.c151 mci_writel(host, TIMING_CON1, HIWORD_UPDATE(raw_value, 0x07ff, 1)); in rockchip_mmc_set_internal_phase()
153 mci_writel(host, TIMING_CON0, HIWORD_UPDATE(raw_value, 0x07ff, 1)); in rockchip_mmc_set_internal_phase()
A Ddw_mmc.h505 #define mci_writel(dev, reg, value) \ macro

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