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Searched refs:mclk (Results 1 – 25 of 160) sorted by relevance

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/drivers/clk/hisilicon/
A Dclk-hi3620.c360 val &= ~(1 << mclk->clken_bit); in mmc_clk_set_timing()
364 val = mmc_clk_delay(val, sam, mclk->sam_off, mclk->sam_bits); in mmc_clk_set_timing()
368 val = mmc_clk_delay(val, drv, mclk->drv_off, mclk->drv_bits); in mmc_clk_set_timing()
372 val = mmc_clk_delay(val, div, mclk->div_off, mclk->div_bits); in mmc_clk_set_timing()
376 val |= 1 << mclk->clken_bit; in mmc_clk_set_timing()
413 struct clk_mmc *mclk; in hisi_register_clk_mmc() local
417 mclk = kzalloc(sizeof(*mclk), GFP_KERNEL); in hisi_register_clk_mmc()
418 if (!mclk) in hisi_register_clk_mmc()
426 mclk->hw.init = &init; in hisi_register_clk_mmc()
428 mclk->id = mmc_clk->id; in hisi_register_clk_mmc()
[all …]
/drivers/gpu/drm/radeon/
A Dbtc_dpm.c2118 mclk = ps->high.mclk; in btc_apply_state_adjust_rules()
2123 mclk = ps->low.mclk; in btc_apply_state_adjust_rules()
2130 ps->low.mclk = mclk; in btc_apply_state_adjust_rules()
2148 mclk = ps->low.mclk; in btc_apply_state_adjust_rules()
2149 if (mclk < ps->medium.mclk) in btc_apply_state_adjust_rules()
2150 mclk = ps->medium.mclk; in btc_apply_state_adjust_rules()
2151 if (mclk < ps->high.mclk) in btc_apply_state_adjust_rules()
2152 mclk = ps->high.mclk; in btc_apply_state_adjust_rules()
2153 ps->low.mclk = mclk; in btc_apply_state_adjust_rules()
2155 ps->medium.mclk = mclk; in btc_apply_state_adjust_rules()
[all …]
A Drv730_dpm.c118 LPRV7XX_SMC_MCLK_VALUE mclk) in rv730_populate_mclk_value() argument
184 mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv730_populate_mclk_value()
185 mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); in rv730_populate_mclk_value()
189 mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss); in rv730_populate_mclk_value()
190 mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in rv730_populate_mclk_value()
332 table->initialState.levels[0].mclk.mclk730.vDLL_CNTL = in rv730_populate_smc_initial_state()
334 table->initialState.levels[0].mclk.mclk730.vMPLL_SS = in rv730_populate_smc_initial_state()
340 cpu_to_be32(initial_state->low.mclk); in rv730_populate_smc_initial_state()
414 state->high.mclk); in rv730_program_memory_timing_parameters()
424 state->medium.mclk); in rv730_program_memory_timing_parameters()
[all …]
A Drv740_dpm.c187 RV7XX_SMC_MCLK_VALUE *mclk) in rv740_populate_mclk_value() argument
274 mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); in rv740_populate_mclk_value()
275 mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); in rv740_populate_mclk_value()
276 mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); in rv740_populate_mclk_value()
277 mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); in rv740_populate_mclk_value()
278 mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); in rv740_populate_mclk_value()
279 mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); in rv740_populate_mclk_value()
280 mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); in rv740_populate_mclk_value()
281 mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1); in rv740_populate_mclk_value()
282 mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2); in rv740_populate_mclk_value()
[all …]
A Drv770_dpm.c389 RV7XX_SMC_MCLK_VALUE *mclk) in rv770_populate_mclk_value() argument
655 pl->mclk, &level->mclk); in rv770_convert_power_level_to_smc()
658 pl->mclk, &level->mclk); in rv770_convert_power_level_to_smc()
661 pl->mclk, &level->mclk); in rv770_convert_power_level_to_smc()
755 state->high.mclk); in rv770_program_memory_timing_parameters()
2182 u32 sclk, mclk; in rv7xx_parse_pplib_clock_info() local
2217 pl->mclk = mclk; in rv7xx_parse_pplib_clock_info()
2262 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in rv7xx_parse_pplib_clock_info()
2537 return pl->mclk; in rv770_dpm_get_current_mclk()
2567 return requested_state->low.mclk; in rv770_dpm_get_mclk()
[all …]
A Dcypress_dpm.c655 u32 mclk, in cypress_populate_mvdd_value() argument
729 pl->mclk, in cypress_convert_power_level_to_smc()
730 &level->mclk, in cypress_convert_power_level_to_smc()
736 pl->mclk, in cypress_convert_power_level_to_smc()
737 &level->mclk, in cypress_convert_power_level_to_smc()
838 if (pl->mclk <= in cypress_convert_mc_reg_table_entry_to_smc()
937 new_state->low.mclk)); in cypress_program_memory_timing_parameters()
940 new_state->medium.mclk)); in cypress_program_memory_timing_parameters()
943 new_state->high.mclk)); in cypress_program_memory_timing_parameters()
1053 range_table->mclk[i]; in cypress_retrieve_ac_timing_for_all_ranges()
[all …]
A Dni_dpm.c791 u32 mclk; in ni_apply_state_adjust_rules() local
808 if (ps->performance_levels[i].mclk > max_limits->mclk) in ni_apply_state_adjust_rules()
809 ps->performance_levels[i].mclk = max_limits->mclk; in ni_apply_state_adjust_rules()
842 mclk = ps->performance_levels[0].mclk; in ni_apply_state_adjust_rules()
845 if (mclk < ps->performance_levels[i].mclk) in ni_apply_state_adjust_rules()
846 mclk = ps->performance_levels[i].mclk; in ni_apply_state_adjust_rules()
851 ps->performance_levels[i].mclk = mclk; in ni_apply_state_adjust_rules()
857 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk; in ni_apply_state_adjust_rules()
1321 u32 mclk, in ni_populate_mvdd_value() argument
3979 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk; in ni_parse_pplib_clock_info()
[all …]
A Dsi_dpm.c2973 if (ps->performance_levels[i].mclk > max_limits->mclk) in si_apply_state_adjust_rules()
2974 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3021 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3042 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3066 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3068 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3069 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3072 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
4154 (mclk <= limits->entries[i].mclk)) in si_populate_phase_shedding_value()
5092 if (state->performance_levels[0].mclk != ulv->pl.mclk) in si_is_state_ulv_compatible()
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/drivers/media/dvb-frontends/
A Dstv0900_sw.c295 u32 mclk, in stv0900_get_symbol_rate() argument
310 intval1 = (mclk) >> 16; in stv0900_get_symbol_rate()
333 symb /= (mclk >> 12); in stv0900_set_symbol_rate()
336 symb /= (mclk >> 10); in stv0900_set_symbol_rate()
339 symb /= (mclk >> 7); in stv0900_set_symbol_rate()
356 symb /= (mclk >> 12); in stv0900_set_max_symbol_rate()
359 symb /= (mclk >> 10); in stv0900_set_max_symbol_rate()
362 symb /= (mclk >> 7); in stv0900_set_max_symbol_rate()
383 symb /= (mclk >> 12); in stv0900_set_min_symbol_rate()
387 symb /= (mclk >> 10); in stv0900_set_min_symbol_rate()
[all …]
A Dstv6110.c28 u32 mclk; member
210 ((((priv->mclk / 1000000) - 16) & 0x1f) << 3); in stv6110_init()
239 freq = divider * (priv->mclk / 1000); in stv6110_get_frequency()
256 frequency, priv->mclk); in stv6110_set_frequency()
261 ((((priv->mclk / 1000000) - 16) & 0x1f) << 3); in stv6110_set_frequency()
290 p_calc = (priv->mclk / 100000); in stv6110_set_frequency()
295 p_calc_opt = (priv->mclk / 100000); in stv6110_set_frequency()
299 ref = priv->mclk / ((1 << (r_div_opt + 1)) * (1 << (p + 1))); in stv6110_set_frequency()
329 vco_freq = divider * ((priv->mclk / 1000) / ((1 << (r_div_opt + 1)))); in stv6110_set_frequency()
417 priv->mclk = config->mclk; in stv6110_attach()
A Dm88rs2000.c104 u32 mclk; in m88rs2000_get_mclk() local
114 mclk = (u32)(reg * RS2000_FE_CRYSTAL_KHZ + 28 / 2) / 28; in m88rs2000_get_mclk()
116 return mclk; in m88rs2000_get_mclk()
122 u32 mclk; in m88rs2000_set_carrieroffset() local
127 mclk = m88rs2000_get_mclk(fe); in m88rs2000_set_carrieroffset()
128 if (!mclk) in m88rs2000_set_carrieroffset()
131 tmp = (offset * 4096 + (s32)mclk / 2) / (s32)mclk; in m88rs2000_set_carrieroffset()
152 u32 mclk; in m88rs2000_set_symbolrate() local
158 mclk = m88rs2000_get_mclk(fe); in m88rs2000_set_symbolrate()
159 if (!mclk) in m88rs2000_set_symbolrate()
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A Dmn88443x.c190 struct clk *mclk; member
213 ret = clk_prepare_enable(chip->mclk); in mn88443x_cmn_power_on()
240 clk_disable_unprepare(chip->mclk); in mn88443x_cmn_power_off()
695 chip->mclk = devm_clk_get(dev, "mclk"); in mn88443x_probe()
696 if (IS_ERR(chip->mclk) && !conf) { in mn88443x_probe()
698 PTR_ERR(chip->mclk)); in mn88443x_probe()
699 return PTR_ERR(chip->mclk); in mn88443x_probe()
718 chip->mclk = conf->mclk; in mn88443x_probe()
744 chip->clk_freq = clk_get_rate(chip->mclk); in mn88443x_probe()
/drivers/iio/adc/
A Dad7766.c38 struct clk *mclk; member
97 ret = clk_prepare_enable(ad7766->mclk); in ad7766_preenable()
121 clk_disable_unprepare(ad7766->mclk); in ad7766_postdisable()
143 *val = clk_get_rate(ad7766->mclk) / in ad7766_read_raw()
224 ad7766->mclk = devm_clk_get(&spi->dev, "mclk"); in ad7766_probe()
225 if (IS_ERR(ad7766->mclk)) in ad7766_probe()
226 return PTR_ERR(ad7766->mclk); in ad7766_probe()
/drivers/gpu/drm/amd/pm/legacy-dpm/
A Dsi_dpm.c3510 ps->performance_levels[i].mclk = max_limits->mclk; in si_apply_state_adjust_rules()
3557 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3578 ps->performance_levels[0].mclk = mclk; in si_apply_state_adjust_rules()
3602 mclk = ps->performance_levels[0].mclk; in si_apply_state_adjust_rules()
3604 if (mclk < ps->performance_levels[i].mclk) in si_apply_state_adjust_rules()
3605 mclk = ps->performance_levels[i].mclk; in si_apply_state_adjust_rules()
3608 ps->performance_levels[i].mclk = mclk; in si_apply_state_adjust_rules()
4694 (mclk <= limits->entries[i].mclk)) in si_populate_phase_shedding_value()
7364 adev->pm.dpm.vce_states[i].mclk = mclk; in si_parse_power_table()
7979 return ((si_cpl1->mclk == si_cpl2->mclk) && in si_are_power_levels_equal()
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/drivers/ufs/host/
A Dufs-mediatek.c148 struct ufs_mtk_clk *mclk = &host->mclk; in ufs_mtk_is_clk_scale_ready() local
150 return mclk->ufs_sel_clki && in ufs_mtk_is_clk_scale_ready()
151 mclk->ufs_sel_max_clki && in ufs_mtk_is_clk_scale_ready()
152 mclk->ufs_sel_min_clki; in ufs_mtk_is_clk_scale_ready()
999 host->mclk.reg_vcore = reg; in ufs_mtk_init_clocks()
1000 host->mclk.vcore_volt = volt; in ufs_mtk_init_clocks()
1774 struct ufs_mtk_clk *mclk = &host->mclk; in _ufs_mtk_clk_scale() local
1788 reg = host->mclk.reg_vcore; in _ufs_mtk_clk_scale()
1789 volt = host->mclk.vcore_volt; in _ufs_mtk_clk_scale()
1793 if (mclk->ufs_fde_max_clki && mclk->ufs_fde_min_clki) in _ufs_mtk_clk_scale()
[all …]
/drivers/spi/
A Dspi-sun4i.c81 struct clk *mclk; member
273 mclk_rate = clk_get_rate(sspi->mclk); in sun4i_spi_transfer_one()
275 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); in sun4i_spi_transfer_one()
276 mclk_rate = clk_get_rate(sspi->mclk); in sun4i_spi_transfer_one()
403 ret = clk_prepare_enable(sspi->mclk); in sun4i_spi_runtime_resume()
425 clk_disable_unprepare(sspi->mclk); in sun4i_spi_runtime_suspend()
485 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); in sun4i_spi_probe()
486 if (IS_ERR(sspi->mclk)) { in sun4i_spi_probe()
488 ret = PTR_ERR(sspi->mclk); in sun4i_spi_probe()
A Dspi-sun6i.c105 struct clk *mclk; member
373 unsigned int mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
377 clk_set_rate(sspi->mclk, 2 * tfr->speed_hz); in sun6i_spi_transfer_one()
378 mclk_rate = clk_get_rate(sspi->mclk); in sun6i_spi_transfer_one()
408 clk_set_rate(sspi->mclk, tfr->speed_hz); in sun6i_spi_transfer_one()
578 ret = clk_prepare_enable(sspi->mclk); in sun6i_spi_runtime_resume()
596 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_resume()
609 clk_disable_unprepare(sspi->mclk); in sun6i_spi_runtime_suspend()
687 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); in sun6i_spi_probe()
688 if (IS_ERR(sspi->mclk)) { in sun6i_spi_probe()
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/drivers/mfd/
A Dsm501.c391 unsigned long mclk; member
407 unsigned long mclk, in sm501_calc_clock() argument
430 clock->mclk = mclk; in sm501_calc_clock()
452 unsigned long mclk; in sm501_calc_pll() local
490 unsigned long mclk; in sm501_select_clock() local
494 for (mclk = 288000000; mclk <= 336000000; mclk += 48000000) { in sm501_select_clock()
551 if (to.mclk != 288000000) in sm501_set_clock()
564 if (to.mclk != 288000000) in sm501_set_clock()
576 if (to.mclk != 288000000) in sm501_set_clock()
1219 if (init->mclk) { in sm501_init_regs()
[all …]
A Dmadera-core.c478 madera->mclk[MADERA_MCLK1].id = "mclk1"; in madera_dev_init()
479 madera->mclk[MADERA_MCLK2].id = "mclk2"; in madera_dev_init()
480 madera->mclk[MADERA_MCLK3].id = "mclk3"; in madera_dev_init()
482 ret = devm_clk_bulk_get_optional(madera->dev, ARRAY_SIZE(madera->mclk), in madera_dev_init()
483 madera->mclk); in madera_dev_init()
490 if (!madera->mclk[MADERA_MCLK2].clk) in madera_dev_init()
717 ret = clk_prepare_enable(madera->mclk[MADERA_MCLK2].clk); in madera_dev_init()
751 clk_disable_unprepare(madera->mclk[MADERA_MCLK2].clk); in madera_dev_init()
786 clk_disable_unprepare(madera->mclk[MADERA_MCLK2].clk); in madera_dev_exit()
/drivers/media/platform/st/stm32/stm32-dcmipp/
A Ddcmipp-core.c43 struct clk *mclk; member
469 struct clk *kclk, *mclk; in dcmipp_probe() local
536 mclk = devm_clk_get(&pdev->dev, "mclk"); in dcmipp_probe()
537 if (IS_ERR(mclk)) in dcmipp_probe()
538 return dev_err_probe(&pdev->dev, PTR_ERR(mclk), in dcmipp_probe()
540 dcmipp->mclk = mclk; in dcmipp_probe()
605 clk_disable_unprepare(dcmipp->mclk); in dcmipp_runtime_suspend()
615 ret = clk_prepare_enable(dcmipp->mclk); in dcmipp_runtime_resume()
623 clk_disable_unprepare(dcmipp->mclk); in dcmipp_runtime_resume()
/drivers/i2c/busses/
A Di2c-bcm2835.c164 struct clk *mclk, in bcm2835_i2c_register_div() argument
174 mclk_name = __clk_get_name(mclk); in bcm2835_i2c_register_div()
411 struct clk *mclk; in bcm2835_i2c_probe() local
425 mclk = devm_clk_get(&pdev->dev, NULL); in bcm2835_i2c_probe()
426 if (IS_ERR(mclk)) in bcm2835_i2c_probe()
427 return dev_err_probe(&pdev->dev, PTR_ERR(mclk), in bcm2835_i2c_probe()
430 i2c_dev->bus_clk = bcm2835_i2c_register_div(&pdev->dev, mclk, i2c_dev); in bcm2835_i2c_probe()
/drivers/staging/iio/frequency/
A Dad9832.c98 struct clk *mclk; member
120 static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout) in ad9832_calc_freqreg() argument
124 do_div(freqreg, mclk); in ad9832_calc_freqreg()
136 clk_freq = clk_get_rate(st->mclk); in ad9832_write_frequency()
326 st->mclk = devm_clk_get_enabled(&spi->dev, "mclk"); in ad9832_probe()
327 if (IS_ERR(st->mclk)) in ad9832_probe()
328 return PTR_ERR(st->mclk); in ad9832_probe()
A Dad9834.c73 struct clk *mclk; member
101 static unsigned int ad9834_calc_freqreg(unsigned long mclk, unsigned long fout) in ad9834_calc_freqreg() argument
105 do_div(freqreg, mclk); in ad9834_calc_freqreg()
115 clk_freq = clk_get_rate(st->mclk); in ad9834_write_frequency()
407 st->mclk = devm_clk_get_enabled(&spi->dev, NULL); in ad9834_probe()
408 if (IS_ERR(st->mclk)) { in ad9834_probe()
410 return PTR_ERR(st->mclk); in ad9834_probe()
/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
A Dramgt215.c458 ram_wr32(fuc, 0x004004, mclk->pll); in gt215_ram_lock_pll()
500 struct gt215_clk_info mclk; in gt215_ram_calc() local
602 pll2pll = (!(ctrl & 0x00000008)) && mclk.pll; in gt215_ram_calc()
615 if (mclk.pll && !pll2pll) { in gt215_ram_calc()
616 ram_mask(fuc, 0x004128, 0x003f3141, mclk.clk | 0x00000101); in gt215_ram_calc()
617 gt215_ram_lock_pll(fuc, &mclk); in gt215_ram_calc()
691 gt215_ram_lock_pll(fuc, &mclk); in gt215_ram_calc()
694 if (mclk.pll) { in gt215_ram_calc()
699 ram_mask(fuc, 0x004168, 0x003f3141, mclk.clk | 0x00000101); in gt215_ram_calc()
737 if (mclk.pll) { in gt215_ram_calc()
[all …]
/drivers/gpu/drm/bridge/
A Dsii902x.c192 struct clk *mclk; member
577 unsigned int mclk) in sii902x_select_mclk_div() argument
579 int div = mclk / rate; in sii902x_select_mclk_div()
689 ret = clk_prepare_enable(sii902x->audio.mclk); in sii902x_audio_hw_params()
695 if (sii902x->audio.mclk) { in sii902x_audio_hw_params()
696 mclk_rate = clk_get_rate(sii902x->audio.mclk); in sii902x_audio_hw_params()
768 clk_disable_unprepare(sii902x->audio.mclk); in sii902x_audio_hw_params()
787 clk_disable_unprepare(sii902x->audio.mclk); in sii902x_audio_shutdown()
903 if (IS_ERR(sii902x->audio.mclk)) { in sii902x_audio_codec_init()
905 __func__, PTR_ERR(sii902x->audio.mclk)); in sii902x_audio_codec_init()
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