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Searched refs:mdc_divider (Results 1 – 2 of 2) sorted by relevance

/drivers/net/ethernet/mediatek/
A Dmtk_eth_soc.h1323 unsigned int mdc_divider; member
A Dmtk_eth_soc.c964 val = FIELD_PREP(PPSC_MDC_CFG, eth->mdc_divider); in mtk_mdio_config()
1012 eth->mdc_divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63); in mtk_mdio_init()
1014 dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / eth->mdc_divider); in mtk_mdio_init()

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