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Searched refs:mdp5_ctl (Results 1 – 9 of 9) sorted by relevance

/drivers/gpu/drm/msm/disp/mdp5/
A Dmdp5_ctl.h26 struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, int intf_num);
28 int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
32 int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_pipeline *p);
33 int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, struct mdp5_pipeline *p,
36 int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
38 int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable);
54 int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
71 u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
73 u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl);
A Dmdp5_ctl.c28 struct mdp5_ctl { struct
72 struct mdp5_ctl ctls[MAX_CTL];
93 u32 ctl_read(struct mdp5_ctl *ctl, u32 reg) in ctl_read()
208 static void send_start_signal(struct mdp5_ctl *ctl) in send_start_signal()
227 int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, in mdp5_ctl_set_encoder_state()
536 u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, in mdp5_ctl_commit()
586 int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl) in mdp5_ctl_get_ctl_id()
594 int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable) in mdp5_ctl_pair()
636 struct mdp5_ctl *ctl = NULL; in mdp5_ctlm_request()
677 struct mdp5_ctl *ctl = &ctl_mgr->ctls[c]; in mdp5_ctlm_hw_reset()
[all …]
A Dmdp5_kms.h120 struct mdp5_ctl *ctl;
167 struct mdp5_ctl *ctl;
280 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc);
292 struct mdp5_interface *intf, struct mdp5_ctl *ctl);
A Dmdp5_encoder.c124 struct mdp5_ctl *ctl = mdp5_encoder->ctl; in mdp5_vid_encoder_disable()
158 struct mdp5_ctl *ctl = mdp5_encoder->ctl; in mdp5_vid_encoder_enable()
223 struct mdp5_ctl *ctl = mdp5_encoder->ctl; in mdp5_encoder_atomic_check()
286 struct mdp5_ctl *ctl) in mdp5_encoder_init()
A Dmdp5_cmd_encoder.c127 struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl; in mdp5_cmd_encoder_disable()
145 struct mdp5_ctl *ctl = mdp5_cmd_enc->ctl; in mdp5_cmd_encoder_enable()
A Dmdp5_crtc.c94 struct mdp5_ctl *ctl = mdp5_cstate->ctl; in crtc_flush()
143 struct mdp5_ctl *ctl = mdp5_cstate->ctl; in complete_flip()
224 struct mdp5_ctl *ctl = mdp5_cstate->ctl; in blend_setup()
959 struct mdp5_ctl *ctl; in mdp5_crtc_cursor_set()
1236 struct mdp5_ctl *ctl = mdp5_cstate->ctl; in mdp5_crtc_wait_for_flush_done()
1276 struct mdp5_ctl *mdp5_crtc_get_ctl(struct drm_crtc *crtc) in mdp5_crtc_get_ctl()
A Dmdp5_kms.c268 struct mdp5_ctl *ctl) in construct_encoder()
306 struct mdp5_ctl *ctl; in modeset_init_intf()
A Dmdp5_plane.c433 struct mdp5_ctl *ctl; in mdp5_plane_atomic_async_update()
/drivers/gpu/drm/msm/
A DMakefile59 disp/mdp5/mdp5_ctl.o \

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