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Searched refs:mem_table (Results 1 – 22 of 22) sorted by relevance

/drivers/net/ethernet/marvell/octeontx2/af/
A Drvu_npc_hash.c448 hash &= table->mem_table.hash_mask; in rvu_exact_calculate_hash()
449 hash += table->mem_table.hash_offset; in rvu_exact_calculate_hash()
472 depth = table->mem_table.depth; in rvu_npc_exact_alloc_mem_table_entry()
493 bitmap_weight(table->mem_table.bmap, table->mem_table.depth)); in rvu_npc_exact_alloc_mem_table_entry()
710 rvu->hw->table->mem_table.mask = mask; in rvu_exact_config_table_mask()
911 depth = table->mem_table.depth; in rvu_npc_exact_dealloc_table_entry()
984 table->mem_table.depth); in rvu_npc_exact_alloc_table_entry()
1423 table->mem_table.depth); in rvu_npc_exact_update_table_entry()
1917 if ((table->mem_table.depth & (table->mem_table.depth - 1)) != 0) { in rvu_npc_exact_init()
1924 table_size = table->mem_table.depth * table->mem_table.ways; in rvu_npc_exact_init()
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A Drvu_npc_hash.h182 } mem_table; member
A Drvu_debugfs.c3559 for (i = 0; i < table->mem_table.ways; i++) { in rvu_dbg_npc_exact_show_entries()
3567 for (i = 0; i < table->mem_table.ways; i++) in rvu_dbg_npc_exact_show_entries()
3573 for (i = 0; i < table->mem_table.depth; i++) { in rvu_dbg_npc_exact_show_entries()
3575 for (j = 0; j < table->mem_table.ways; j++) { in rvu_dbg_npc_exact_show_entries()
3590 for (j = 0; j < table->mem_table.ways; j++) { in rvu_dbg_npc_exact_show_entries()
3647 seq_printf(s, "Ways : %d\n", table->mem_table.ways); in rvu_dbg_npc_exact_show_info()
3648 seq_printf(s, "Depth : %d\n", table->mem_table.depth); in rvu_dbg_npc_exact_show_info()
3649 seq_printf(s, "Mask : 0x%llx\n", table->mem_table.mask); in rvu_dbg_npc_exact_show_info()
3650 seq_printf(s, "Hash Mask : 0x%x\n", table->mem_table.hash_mask); in rvu_dbg_npc_exact_show_info()
3651 seq_printf(s, "Hash Offset : 0x%x\n", table->mem_table.hash_offset); in rvu_dbg_npc_exact_show_info()
/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
A Dvega20_hwmgr.c621 dpm_table = &(data->dpm_table.mem_table); in vega20_setup_memclk_dpm_table()
673 dpm_table = &(data->dpm_table.mem_table); in vega20_setup_default_dpm_tables()
1078 data->dpm_table.mem_table.dpm_levels[data->dpm_table.mem_table.count - 2].value; in vega20_od8_set_feature_capabilities()
1527 &(data->dpm_table.mem_table); in vega20_get_mclk_od()
1529 &(data->golden_dpm_table.mem_table); in vega20_get_mclk_od()
1546 &(data->golden_dpm_table.mem_table); in vega20_set_mclk_od()
1572 struct vega20_single_dpm_table *mem_table = &(data->dpm_table.mem_table); in vega20_populate_umdpstate_clocks() local
1584 hwmgr->pstate_mclk_peak = mem_table->dpm_levels[mem_table->count - 1].value; in vega20_populate_umdpstate_clocks()
2353 &data->dpm_table.mem_table; in vega20_notify_smc_display_config_after_ps_adjustment()
2608 data->dpm_table.mem_table.count - 1); in vega20_force_clock_level()
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A Dvega12_hwmgr.c680 dpm_table = &(data->dpm_table.mem_table); in vega12_setup_default_dpm_tables()
1669 data->dpm_table.mem_table.dpm_state.soft_min_level = in vega12_force_dpm_highest()
1670 data->dpm_table.mem_table.dpm_state.soft_max_level = in vega12_force_dpm_highest()
1698 data->dpm_table.mem_table.dpm_state.soft_min_level = in vega12_force_dpm_lowest()
1699 data->dpm_table.mem_table.dpm_state.soft_max_level = in vega12_force_dpm_lowest()
1898 dpm_table = &(data->dpm_table.mem_table); in vega12_get_memclocks()
2396 dpm_table = &(data->dpm_table.mem_table); in vega12_apply_clocks_adjust_rules()
2554 &data->dpm_table.mem_table); in vega12_pre_display_configuration_changed_task()
2681 for (i = 0; i < dpm_table->mem_table.count; i++) {
2682 if (dpm_table->mem_table.dpm_levels[i].enabled &&
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A Dvega10_hwmgr.c1371 data->dpm_table.mem_table.count = 0; in vega10_setup_default_dpm_tables()
1372 dpm_table = &(data->dpm_table.mem_table); in vega10_setup_default_dpm_tables()
1883 &(data->dpm_table.mem_table); in vega10_populate_all_memory_levels()
3585 &(data->dpm_table.mem_table), in vega10_trim_dpm_states()
3676 data->dpm_table.mem_table.dpm_state.soft_min_level = in vega10_upload_dpm_bootup_level()
3969 if (mclk_idx < dpm_table->mem_table.count) { in vega10_read_sensor()
5206 &(data->golden_dpm_table.mem_table); in vega10_get_mclk_od()
5221 &(data->golden_dpm_table.mem_table); in vega10_set_mclk_od()
5442 golden_table = &(data->golden_dpm_table.mem_table); in vega10_check_clk_voltage_valid()
5467 &data->dpm_table.mem_table; in vega10_odn_update_power_state()
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A Dvega10_hwmgr.h149 struct vega10_single_dpm_table mem_table; member
A Dvega12_hwmgr.h127 struct vega12_single_dpm_table mem_table; member
A Dvega20_hwmgr.h180 struct vega20_single_dpm_table mem_table; member
/drivers/gpu/drm/amd/pm/swsmu/smu11/
A Darcturus_ppt.h62 struct arcturus_single_dpm_table mem_table; member
A Darcturus_ppt.c577 struct smu_11_0_dpm_table *mem_table = in arcturus_populate_umd_state_clk() local
587 pstate_table->uclk_pstate.min = mem_table->min; in arcturus_populate_umd_state_clk()
588 pstate_table->uclk_pstate.peak = mem_table->max; in arcturus_populate_umd_state_clk()
594 mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL && in arcturus_populate_umd_state_clk()
599 mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value; in arcturus_populate_umd_state_clk()
A Dsmu_v11_0.c1859 struct smu_11_0_dpm_table *mem_table = in smu_v11_0_set_performance_level() local
1875 mclk_min = mclk_max = mem_table->max; in smu_v11_0_set_performance_level()
1880 mclk_min = mclk_max = mem_table->min; in smu_v11_0_set_performance_level()
1886 mclk_min = mem_table->min; in smu_v11_0_set_performance_level()
1887 mclk_max = mem_table->max; in smu_v11_0_set_performance_level()
A Dnavi10_ppt.c1715 struct smu_11_0_dpm_table *mem_table = in navi10_populate_umd_state_clk() local
1773 pstate_table->uclk_pstate.min = mem_table->min; in navi10_populate_umd_state_clk()
1774 pstate_table->uclk_pstate.peak = mem_table->max; in navi10_populate_umd_state_clk()
1780 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK && in navi10_populate_umd_state_clk()
A Dsienna_cichlid_ppt.c1491 struct smu_11_0_dpm_table *mem_table = in sienna_cichlid_populate_umd_state_clk() local
1502 pstate_table->uclk_pstate.min = mem_table->min; in sienna_cichlid_populate_umd_state_clk()
1503 pstate_table->uclk_pstate.peak = mem_table->max; in sienna_cichlid_populate_umd_state_clk()
/drivers/gpu/drm/amd/pm/swsmu/smu13/
A Daldebaran_ppt.h62 struct aldebaran_single_dpm_table mem_table; member
A Daldebaran_ppt.c598 struct smu_13_0_dpm_table *mem_table = in aldebaran_populate_umd_state_clk() local
610 pstate_table->uclk_pstate.min = mem_table->min; in aldebaran_populate_umd_state_clk()
611 pstate_table->uclk_pstate.peak = mem_table->max; in aldebaran_populate_umd_state_clk()
612 pstate_table->uclk_pstate.curr.min = mem_table->min; in aldebaran_populate_umd_state_clk()
613 pstate_table->uclk_pstate.curr.max = mem_table->max; in aldebaran_populate_umd_state_clk()
621 mem_table->count > ALDEBARAN_UMD_PSTATE_MCLK_LEVEL && in aldebaran_populate_umd_state_clk()
626 mem_table->dpm_levels[ALDEBARAN_UMD_PSTATE_MCLK_LEVEL].value; in aldebaran_populate_umd_state_clk()
A Dsmu_v13_0.c1589 struct smu_13_0_dpm_table *mem_table = in smu_v13_0_set_performance_level() local
1614 mclk_min = mclk_max = mem_table->max; in smu_v13_0_set_performance_level()
1622 mclk_min = mclk_max = mem_table->min; in smu_v13_0_set_performance_level()
1631 mclk_min = mem_table->min; in smu_v13_0_set_performance_level()
1632 mclk_max = mem_table->max; in smu_v13_0_set_performance_level()
A Dsmu_v13_0_6_ppt.c1108 struct smu_13_0_dpm_table *mem_table = in smu_v13_0_6_populate_umd_state_clk() local
1119 pstate_table->uclk_pstate.min = mem_table->min; in smu_v13_0_6_populate_umd_state_clk()
1120 pstate_table->uclk_pstate.peak = mem_table->max; in smu_v13_0_6_populate_umd_state_clk()
1121 pstate_table->uclk_pstate.curr.min = mem_table->min; in smu_v13_0_6_populate_umd_state_clk()
1122 pstate_table->uclk_pstate.curr.max = mem_table->max; in smu_v13_0_6_populate_umd_state_clk()
1130 mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL && in smu_v13_0_6_populate_umd_state_clk()
1135 mem_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL].value; in smu_v13_0_6_populate_umd_state_clk()
A Dsmu_v13_0_7_ppt.c2293 struct smu_13_0_dpm_table *mem_table = in smu_v13_0_7_populate_umd_state_clk() local
2317 pstate_table->uclk_pstate.min = mem_table->min; in smu_v13_0_7_populate_umd_state_clk()
2318 pstate_table->uclk_pstate.peak = mem_table->max; in smu_v13_0_7_populate_umd_state_clk()
2337 pstate_table->uclk_pstate.standard = mem_table->max; in smu_v13_0_7_populate_umd_state_clk()
A Dsmu_v13_0_0_ppt.c2307 struct smu_13_0_dpm_table *mem_table = in smu_v13_0_0_populate_umd_state_clk() local
2331 pstate_table->uclk_pstate.min = mem_table->min; in smu_v13_0_0_populate_umd_state_clk()
2332 pstate_table->uclk_pstate.peak = mem_table->max; in smu_v13_0_0_populate_umd_state_clk()
2351 pstate_table->uclk_pstate.standard = mem_table->max; in smu_v13_0_0_populate_umd_state_clk()
/drivers/gpu/drm/amd/pm/swsmu/smu14/
A Dsmu_v14_0.c1252 struct smu_14_0_dpm_table *mem_table = in smu_v14_0_set_performance_level() local
1277 mclk_min = mclk_max = mem_table->max; in smu_v14_0_set_performance_level()
1285 mclk_min = mclk_max = mem_table->min; in smu_v14_0_set_performance_level()
1294 mclk_min = mem_table->min; in smu_v14_0_set_performance_level()
1295 mclk_max = mem_table->max; in smu_v14_0_set_performance_level()
A Dsmu_v14_0_2_ppt.c1587 struct smu_14_0_dpm_table *mem_table = in smu_v14_0_2_populate_umd_state_clk() local
1611 pstate_table->uclk_pstate.min = mem_table->min; in smu_v14_0_2_populate_umd_state_clk()
1612 pstate_table->uclk_pstate.peak = mem_table->max; in smu_v14_0_2_populate_umd_state_clk()
1631 pstate_table->uclk_pstate.standard = mem_table->max; in smu_v14_0_2_populate_umd_state_clk()

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