| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.c | 372 unsigned int meta_req_height; in get_meta_and_pte_attr() local
491 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
502 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
503 + meta_req_height; in get_meta_and_pte_attr()
504 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
550 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| A D | display_rq_dlg_calc_20v2.c | 372 unsigned int meta_req_height; in get_meta_and_pte_attr() local
491 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
502 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
503 + meta_req_height; in get_meta_and_pte_attr()
504 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
550 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 362 unsigned int meta_req_height; in get_meta_and_pte_attr() local
485 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
496 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
497 + meta_req_height; in get_meta_and_pte_attr()
498 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
547 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| A D | display_mode_vba_21.c | 438 unsigned int meta_req_height[],
1963 &locals->meta_req_height[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2527 locals->meta_req_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4679 &locals->meta_req_height[k], in dml21_ModeSupportAndSystemConfigurationFull()
5856 unsigned int meta_req_height[], in CalculateMetaAndPTETimes()
5933 - meta_req_height[k]; in CalculateMetaAndPTETimes()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 318 unsigned int meta_req_height = 0; in get_meta_and_pte_attr() local
464 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
475 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_meta_and_pte_attr()
476 + meta_req_height; in get_meta_and_pte_attr()
477 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
523 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| A D | display_mode_vba_30.c | 459 int meta_req_height[],
2266 &v->meta_req_height[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2870 v->meta_req_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5673 int meta_req_height[], in CalculateMetaAndPTETimes() argument
5743 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k]; in CalculateMetaAndPTETimes()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 341 unsigned int meta_req_height; in get_meta_and_pte_attr() local
481 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
491 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) + meta_req_height; in get_meta_and_pte_attr()
492 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
524 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| A D | display_mode_vba_31.c | 423 int meta_req_height[],
2397 &v->meta_req_height[k],
3031 v->meta_req_height,
6044 int meta_req_height[], argument
6114 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | dml1_display_rq_dlg_calc.c | 583 unsigned int meta_req_height; in get_surf_rq_param() local
726 meta_req_height = 1 << log2_meta_req_height; in get_surf_rq_param()
740 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) in get_surf_rq_param()
741 + meta_req_height; in get_surf_rq_param()
742 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_surf_rq_param()
783 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_surf_rq_param()
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| A D | display_mode_vba.h | 831 unsigned int meta_req_height[DC__NUM_DPP__MAX]; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_rq_dlg_calc_314.c | 429 unsigned int meta_req_height; in get_meta_and_pte_attr() local
569 meta_req_height = 1 << log2_meta_req_height; in get_meta_and_pte_attr()
579 meta_row_width_ub = dml_round_to_multiple(vp_height - 1, meta_req_height, 1) + meta_req_height; in get_meta_and_pte_attr()
580 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_height; in get_meta_and_pte_attr()
612 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height; in get_meta_and_pte_attr()
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| A D | display_mode_vba_314.c | 432 int meta_req_height[],
2416 &v->meta_req_height[k],
3050 v->meta_req_height,
6139 int meta_req_height[], argument
6209 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k];
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.h | 399 unsigned int meta_req_height[],
914 unsigned int meta_req_height[],
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| A D | display_mode_vba_util_32.c | 1940 unsigned int meta_req_height[], in dml32_CalculateVMRowAndSwath()
2130 &meta_req_height[k], in dml32_CalculateVMRowAndSwath()
4895 unsigned int meta_req_height[], in dml32_CalculateMetaAndPTETimes()
4965 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k]; in dml32_CalculateMetaAndPTETimes()
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| A D | display_mode_vba_32.c | 495 v->meta_req_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1311 v->meta_req_height, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared_types.h | 501 unsigned int meta_req_height[DML2_MAX_PLANES]; member
747 unsigned int meta_req_height[DML2_MAX_PLANES]; member
1670 unsigned int *meta_req_height; member
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| A D | dml2_core_dcn4_calcs.c | 9748 meta_chunk_threshold = 2 * min_meta_chunk_width - p->meta_req_height[k]; in CalculateMetaAndPTETimes()
10756 CalculateVMRowAndSwath_params->meta_req_height_luma = mode_lib->mp.meta_req_height; in dml_core_mode_programming()
11780 CalculateMetaAndPTETimes_params->meta_req_height = mode_lib->mp.meta_req_height; in dml_core_mode_programming()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_core_structs.h | 1066 dml_uint_t meta_req_height[__DML_NUM_PLANES__]; member
1423 dml_uint_t *meta_req_height; member
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| A D | display_mode_core.c | 518 dml_uint_t meta_req_height[],
3445 dml_uint_t meta_req_height[], in CalculateMetaAndPTETimes()
3516 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_height[k]; in CalculateMetaAndPTETimes()
5192 &p->meta_req_height[k], in CalculateVMRowAndSwath()
7715 CalculateVMRowAndSwath_params->meta_req_height = s->dummy_integer_array[6]; in dml_core_mode_support()
8727 CalculateVMRowAndSwath_params->meta_req_height = locals->meta_req_height; in dml_core_mode_programming()
9558 locals->meta_req_height, in dml_core_mode_programming()
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