| /drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| A D | display_rq_dlg_calc_20.c | 371 unsigned int meta_req_width; in get_meta_and_pte_attr() local
490 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
497 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
498 + meta_req_width; in get_meta_and_pte_attr()
499 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
548 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| A D | display_rq_dlg_calc_20v2.c | 371 unsigned int meta_req_width; in get_meta_and_pte_attr() local
490 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
497 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
498 + meta_req_width; in get_meta_and_pte_attr()
499 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
548 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn21/ |
| A D | display_rq_dlg_calc_21.c | 361 unsigned int meta_req_width; in get_meta_and_pte_attr() local
484 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
491 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
492 + meta_req_width; in get_meta_and_pte_attr()
493 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
545 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| A D | display_mode_vba_21.c | 437 unsigned int meta_req_width[],
1962 &locals->meta_req_width[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2526 locals->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
4678 &locals->meta_req_width[k], in dml21_ModeSupportAndSystemConfigurationFull()
5855 unsigned int meta_req_width[], in CalculateMetaAndPTETimes() argument
5930 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; in CalculateMetaAndPTETimes()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| A D | display_rq_dlg_calc_30.c | 317 unsigned int meta_req_width = 0; in get_meta_and_pte_attr() local
463 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
470 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_meta_and_pte_attr()
471 + meta_req_width; in get_meta_and_pte_attr()
472 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
521 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| A D | display_mode_vba_30.c | 457 int meta_req_width[],
2265 &v->meta_req_width[k], in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
2868 v->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
5671 int meta_req_width[], in CalculateMetaAndPTETimes() argument
5741 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; in CalculateMetaAndPTETimes()
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| /drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| A D | display_rq_dlg_calc_31.c | 340 unsigned int meta_req_width; in get_meta_and_pte_attr() local
480 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
487 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) + meta_req_width; in get_meta_and_pte_attr()
488 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
522 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| A D | display_mode_vba_31.c | 421 int meta_req_width[],
2396 &v->meta_req_width[k],
3029 v->meta_req_width,
6042 int meta_req_width[], argument
6112 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
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| /drivers/gpu/drm/amd/display/dc/dml/ |
| A D | dml1_display_rq_dlg_calc.c | 582 unsigned int meta_req_width; in get_surf_rq_param() local
725 meta_req_width = 1 << log2_meta_req_width; in get_surf_rq_param()
735 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) in get_surf_rq_param()
736 + meta_req_width; in get_surf_rq_param()
737 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_surf_rq_param()
781 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_surf_rq_param()
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| A D | display_mode_vba.h | 832 unsigned int meta_req_width[DC__NUM_DPP__MAX]; member
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| /drivers/gpu/drm/amd/display/dc/dml/dcn314/ |
| A D | display_rq_dlg_calc_314.c | 428 unsigned int meta_req_width; in get_meta_and_pte_attr() local
568 meta_req_width = 1 << log2_meta_req_width; in get_meta_and_pte_attr()
575 meta_row_width_ub = dml_round_to_multiple(vp_width - 1, meta_req_width, 1) + meta_req_width; in get_meta_and_pte_attr()
576 rq_dlg_param->meta_req_per_row_ub = meta_row_width_ub / meta_req_width; in get_meta_and_pte_attr()
610 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width; in get_meta_and_pte_attr()
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| A D | display_mode_vba_314.c | 430 int meta_req_width[],
2415 &v->meta_req_width[k],
3048 v->meta_req_width,
6137 int meta_req_width[], argument
6207 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k];
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| /drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| A D | display_mode_vba_util_32.h | 397 unsigned int meta_req_width[],
912 unsigned int meta_req_width[],
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| A D | display_mode_vba_util_32.c | 1938 unsigned int meta_req_width[], in dml32_CalculateVMRowAndSwath()
2129 &meta_req_width[k], in dml32_CalculateVMRowAndSwath()
4893 unsigned int meta_req_width[], in dml32_CalculateMetaAndPTETimes() argument
4963 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; in dml32_CalculateMetaAndPTETimes()
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| A D | display_mode_vba_32.c | 493 v->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1309 v->meta_req_width, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_shared_types.h | 491 unsigned int meta_req_width[DML2_MAX_PLANES]; member
746 unsigned int meta_req_width[DML2_MAX_PLANES]; member
1668 unsigned int *meta_req_width; member
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| A D | dml2_core_dcn4_calcs.c | 9746 meta_chunk_threshold = 2 * min_meta_chunk_width - p->meta_req_width[k]; in CalculateMetaAndPTETimes()
10755 CalculateVMRowAndSwath_params->meta_req_width_luma = mode_lib->mp.meta_req_width; in dml_core_mode_programming()
11778 CalculateMetaAndPTETimes_params->meta_req_width = mode_lib->mp.meta_req_width; in dml_core_mode_programming()
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| /drivers/gpu/drm/amd/display/dc/dml2/ |
| A D | display_mode_core_structs.h | 1065 dml_uint_t meta_req_width[__DML_NUM_PLANES__]; member
1421 dml_uint_t *meta_req_width; member
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| A D | display_mode_core.c | 516 dml_uint_t meta_req_width[],
3443 dml_uint_t meta_req_width[], in CalculateMetaAndPTETimes() argument
3514 meta_chunk_threshold = 2 * min_meta_chunk_width - meta_req_width[k]; in CalculateMetaAndPTETimes()
5191 &p->meta_req_width[k], in CalculateVMRowAndSwath()
7713 CalculateVMRowAndSwath_params->meta_req_width = s->dummy_integer_array[4]; in dml_core_mode_support()
8725 CalculateVMRowAndSwath_params->meta_req_width = locals->meta_req_width; in dml_core_mode_programming()
9556 locals->meta_req_width, in dml_core_mode_programming()
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