Home
last modified time | relevance | path

Searched refs:mhz (Results 1 – 25 of 30) sorted by relevance

12

/drivers/phy/intel/
A Dphy-intel-keembay-emmc.c59 unsigned int mhz; in keembay_emmc_phy_power() local
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
85 if (mhz <= 200 && mhz >= 170) in keembay_emmc_phy_power()
87 else if (mhz <= 170 && mhz >= 140) in keembay_emmc_phy_power()
89 else if (mhz <= 140 && mhz >= 110) in keembay_emmc_phy_power()
91 else if (mhz <= 110 && mhz >= 80) in keembay_emmc_phy_power()
93 else if (mhz <= 80 && mhz >= 50) in keembay_emmc_phy_power()
99 if (mhz > 175) in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
156 if (mhz == 0) in keembay_emmc_phy_power()
/drivers/gpu/drm/amd/display/dc/
A Ddm_pp_smu.h119 void (*set_hard_min_dcfclk_by_freq)(struct pp_smu *pp, int mhz);
125 void (*set_min_deep_sleep_dcfclk)(struct pp_smu *pp, int mhz);
130 void (*set_hard_min_fclk_by_freq)(struct pp_smu *pp, int mhz);
135 void (*set_hard_min_socclk_by_freq)(struct pp_smu *pp, int mhz);
/drivers/gpu/drm/amd/display/amdgpu_dm/
A Damdgpu_dm_pp_smu.c545 static void pp_rv_set_hard_min_fclk_by_freq(struct pp_smu *pp, int mhz) in pp_rv_set_hard_min_fclk_by_freq() argument
550 amdgpu_dpm_set_hard_min_fclk_by_freq(adev, mhz); in pp_rv_set_hard_min_fclk_by_freq()
581 pp_nv_set_min_deep_sleep_dcfclk(struct pp_smu *pp, int mhz) in pp_nv_set_min_deep_sleep_dcfclk() argument
588 ret = amdgpu_dpm_set_min_deep_sleep_dcefclk(adev, mhz); in pp_nv_set_min_deep_sleep_dcfclk()
598 struct pp_smu *pp, int mhz) in pp_nv_set_hard_min_dcefclk_by_freq() argument
606 clock_req.clock_freq_in_khz = mhz * 1000; in pp_nv_set_hard_min_dcefclk_by_freq()
621 pp_nv_set_hard_min_uclk_by_freq(struct pp_smu *pp, int mhz) in pp_nv_set_hard_min_uclk_by_freq() argument
629 clock_req.clock_freq_in_khz = mhz * 1000; in pp_nv_set_hard_min_uclk_by_freq()
657 enum pp_smu_nv_clock_id clock_id, int mhz) in pp_nv_set_voltage_by_freq() argument
677 clock_req.clock_freq_in_khz = mhz * 1000; in pp_nv_set_voltage_by_freq()
/drivers/mmc/host/
A Dsdhci-of-arasan.c1207 u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000); in sdhci_arasan_update_baseclkfreq() local
1220 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); in sdhci_arasan_update_baseclkfreq()
1781 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000); in sdhci_zynqmp_set_dynamic_config()
1782 if (mhz > 100 && mhz <= 200) in sdhci_zynqmp_set_dynamic_config()
1783 mhz = 200; in sdhci_zynqmp_set_dynamic_config()
1784 else if (mhz > 50 && mhz <= 100) in sdhci_zynqmp_set_dynamic_config()
1785 mhz = 100; in sdhci_zynqmp_set_dynamic_config()
1786 else if (mhz > 25 && mhz <= 50) in sdhci_zynqmp_set_dynamic_config()
1787 mhz = 50; in sdhci_zynqmp_set_dynamic_config()
1789 mhz = 25; in sdhci_zynqmp_set_dynamic_config()
[all …]
/drivers/net/wireless/intel/iwlwifi/mld/
A Dlink.c679 int mhz = nl80211_chan_width_to_mhz(chan_width); in iwl_mld_get_n_subchannels() local
682 if (WARN_ONCE(mhz < 20 || mhz > 320, in iwl_mld_get_n_subchannels()
683 "Invalid channel width : (%d)\n", mhz)) in iwl_mld_get_n_subchannels()
687 n_subchannels = mhz / 20; in iwl_mld_get_n_subchannels()
690 if (mhz >= 80) in iwl_mld_get_n_subchannels()
/drivers/iio/filter/
A Dadmv8818.c733 u32 mhz; in admv8818_read_properties() local
736 ret = device_property_read_u32(&spi->dev, "adi,lpf-margin-mhz", &mhz); in admv8818_read_properties()
738 st->lpf_margin_hz = (u64)mhz * HZ_PER_MHZ; in admv8818_read_properties()
745 ret = device_property_read_u32(&spi->dev, "adi,hpf-margin-mhz", &mhz); in admv8818_read_properties()
747 st->hpf_margin_hz = (u64)mhz * HZ_PER_MHZ; in admv8818_read_properties()
/drivers/scsi/
A Dwd33c93.h149 #define WD33C93_FS_MHZ(mhz) (mhz) argument
A Desp_scsi.h246 #define ESP_NEG_DEFP(mhz, cfact) \ argument
247 ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
A Dwd33c93.c1808 calc_sx_table(unsigned int mhz, struct sx_period sx_table[9]) in calc_sx_table() argument
1811 if (mhz < 11) in calc_sx_table()
1813 else if (mhz < 16) in calc_sx_table()
1818 d = (100000 * d) / 2 / mhz; /* 100 x DTCC / nanosec */ in calc_sx_table()
1835 set_clk_freq(int freq, int *mhz) in set_clk_freq() argument
1855 *mhz = freq; in set_clk_freq()
/drivers/gpu/drm/sprd/
A Dmegacores_pll.c33 const u32 mhz = 1000000; in dphy_calc_pll_param() local
66 tmp = pll->fvco * factor * mhz; in dphy_calc_pll_param()
68 tmp = tmp - pll->nint * factor * mhz; in dphy_calc_pll_param()
/drivers/cpufreq/
A Dspeedstep-centrino.c85 #define OP(mhz, mv) \ argument
87 .frequency = (mhz) * 1000, \
88 .driver_data = (((mhz)/100) << 8) | ((mv - 700) / 16) \
/drivers/acpi/
A Dcppc_acpi.c1932 u16 *mhz = (u16 *)private; in cppc_find_dmi_mhz() local
1938 *mhz = umax(val, *mhz); in cppc_find_dmi_mhz()
1945 u16 mhz = 0; in cppc_get_dmi_max_khz() local
1947 dmi_walk(cppc_find_dmi_mhz, &mhz); in cppc_get_dmi_max_khz()
1953 mhz = mhz ? mhz : 1; in cppc_get_dmi_max_khz()
1955 return KHZ_PER_MHZ * mhz; in cppc_get_dmi_max_khz()
/drivers/gpu/drm/nouveau/nvkm/subdev/bios/
A Drammap.c133 nvbios_rammapEm(struct nvkm_bios *bios, u16 mhz, in nvbios_rammapEm() argument
139 if (mhz >= info->rammap_min && mhz <= info->rammap_max) in nvbios_rammapEm()
/drivers/net/wireless/intel/iwlwifi/mvm/
A Dlink.c441 int mhz = nl80211_chan_width_to_mhz(chan_width); in iwl_mvm_get_puncturing_factor() local
444 if (WARN_ONCE(mhz < 20 || mhz > 320, in iwl_mvm_get_puncturing_factor()
445 "Invalid channel width : (%d)\n", mhz)) in iwl_mvm_get_puncturing_factor()
449 if (mhz < 80) in iwl_mvm_get_puncturing_factor()
453 n_subchannels = mhz / 20; in iwl_mvm_get_puncturing_factor()
/drivers/media/i2c/
A Dimx283.c258 unsigned int mhz; member
265 .mhz = 6 * HZ_PER_MHZ,
275 .mhz = 12 * HZ_PER_MHZ,
285 .mhz = 18 * HZ_PER_MHZ,
295 .mhz = 24 * HZ_PER_MHZ,
1001 imx283->freq->mhz / HZ_PER_MHZ); in imx283_standby_cancel()
1473 if (xclk_freq == imx283_frequencies[i].mhz) { in imx283_probe()
/drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/
A Drammap.h15 u32 nvbios_rammapEm(struct nvkm_bios *, u16 mhz,
/drivers/gpu/drm/nouveau/nvkm/subdev/fb/
A Dramgk104.c966 u32 mhz = khz / 1000; in gk104_ram_calc_data() local
969 if (mhz >= cfg->bios.rammap_min && in gk104_ram_calc_data()
970 mhz <= cfg->bios.rammap_max) { in gk104_ram_calc_data()
977 nvkm_error(subdev, "ramcfg data for %dMHz not found\n", mhz); in gk104_ram_calc_data()
1159 u32 mhz = freq / 1000; in gk104_ram_prog_0() local
1163 if (mhz >= cfg->bios.rammap_min && in gk104_ram_prog_0()
1164 mhz <= cfg->bios.rammap_max) in gk104_ram_prog_0()
/drivers/clk/
A Dclk-lmk04832.c427 unsigned long mhz = rate / 1000000; in lmk04832_check_vco_ranges() local
431 if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1]) in lmk04832_check_vco_ranges()
434 if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1]) in lmk04832_check_vco_ranges()
/drivers/iio/light/
A Dvl6180.c474 static int vl6180_meas_reg_val_from_mhz(unsigned int mhz) in vl6180_meas_reg_val_from_mhz() argument
476 unsigned int period = DIV_ROUND_CLOSEST(1000 * 1000, mhz); in vl6180_meas_reg_val_from_mhz()
/drivers/media/cec/usb/extron-da-hd-4k-plus/
A Dextron-da-hd-4k-plus.c268 unsigned int mhz; in extron_parse_edid() local
282 mhz = div_u64(pclk, w * h); in extron_parse_edid()
283 if (mhz >= 297) in extron_parse_edid()
285 if (mhz >= 594) in extron_parse_edid()
/drivers/net/wireless/ath/ath11k/
A Dreg.c179 ch->mhz = channel->center_freq; in ath11k_reg_update_chan_list()
199 ch->mhz, ch->maxpower, ch->maxregpower, in ath11k_reg_update_chan_list()
A Dwmi.h2713 u32 mhz; member
3505 u32 mhz; member
/drivers/net/wireless/ath/ath12k/
A Dreg.c210 ch->mhz = channel->center_freq; in ath12k_reg_update_chan_list()
230 ch->mhz, ch->maxpower, ch->maxregpower, in ath12k_reg_update_chan_list()
/drivers/net/wireless/ath/wcn36xx/
A Dsmd.c957 param->mhz = req->channels[i]->center_freq; in wcn36xx_smd_update_channel_list()
994 __func__, param->mhz, param->channel_info, param->reg_info_1, in wcn36xx_smd_update_channel_list()
A Dhal.h1373 u32 mhz; member

Completed in 139 milliseconds

12