Home
last modified time | relevance | path

Searched refs:miig_rt (Results 1 – 9 of 9) sorted by relevance

/drivers/net/ethernet/ti/icssg/
A Dicssg_classifier.c212 regmap_write(miig_rt, offset, val); in rx_class_ft1_set_start_len()
265 regmap_write(miig_rt, offset, data); in rx_class_set_and()
274 regmap_write(miig_rt, offset, data); in rx_class_set_or()
282 regmap_read(miig_rt, offset, &val); in rx_class_get_or()
337 rx_class_set_or(miig_rt, slice, n, 0); in icssg_class_disable()
344 regmap_read(miig_rt, offset, &data); in icssg_class_disable()
349 regmap_write(miig_rt, offset, data); in icssg_class_disable()
375 icssg_class_disable(miig_rt, slice); in icssg_class_default()
404 icssg_class_disable(miig_rt, slice); in icssg_class_promiscuous_sr1()
410 regmap_read(miig_rt, offset, &data); in icssg_class_promiscuous_sr1()
[all …]
A Dicssg_mii_cfg.c45 void icssg_update_rgmii_cfg(struct regmap *miig_rt, struct prueth_emac *emac) in icssg_update_rgmii_cfg() argument
55 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, gig_en_mask, gig_val); in icssg_update_rgmii_cfg()
61 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, inband_en_mask, inband_val); in icssg_update_rgmii_cfg()
67 regmap_update_bits(miig_rt, RGMII_CFG_OFFSET, full_duplex_mask, in icssg_update_rgmii_cfg()
84 regmap_update_bits(miig_rt, ICSSG_CFG_OFFSET, mask, val); in icssg_miig_set_interface_mode()
85 regmap_read(miig_rt, ICSSG_CFG_OFFSET, &val); in icssg_miig_set_interface_mode()
92 regmap_read(miig_rt, RGMII_CFG_OFFSET, &val); in icssg_rgmii_cfg_get_bitfield()
99 u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii) in icssg_rgmii_get_speed() argument
108 return icssg_rgmii_cfg_get_bitfield(miig_rt, mask, shift); in icssg_rgmii_get_speed()
112 u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii) in icssg_rgmii_get_fullduplex() argument
[all …]
A Dicssg_queues.c23 regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &cnt); in icssg_queue_pop()
27 regmap_read(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, &val); in icssg_queue_pop()
38 regmap_write(prueth->miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, addr); in icssg_queue_push()
49 regmap_read(prueth->miig_rt, ICSSG_QUEUE_CNT_OFFSET + 4 * queue, &reg); in icssg_queue_level()
A Dicssg_mii_rt.h145 void icssg_update_rgmii_cfg(struct regmap *miig_rt, struct prueth_emac *emac);
146 u32 icssg_rgmii_cfg_get_bitfield(struct regmap *miig_rt, u32 mask, u32 shift);
147 u32 icssg_rgmii_get_speed(struct regmap *miig_rt, int mii);
148 u32 icssg_rgmii_get_fullduplex(struct regmap *miig_rt, int mii);
149 void icssg_miig_set_interface_mode(struct regmap *miig_rt, int mii, phy_interface_t phy_if);
A Dicssg_prueth.h325 struct regmap *miig_rt; member
404 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac);
405 void icssg_class_set_host_mac_addr(struct regmap *miig_rt, const u8 *mac);
406 void icssg_class_disable(struct regmap *miig_rt, int slice);
407 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti,
409 void icssg_class_promiscuous_sr1(struct regmap *miig_rt, int slice);
410 void icssg_class_add_mcast_sr1(struct regmap *miig_rt, int slice,
412 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr);
A Dicssg_config.c167 struct regmap *miig_rt = prueth->miig_rt; in icssg_miig_queues_init() local
178 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); in icssg_miig_queues_init()
183 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, queue); in icssg_miig_queues_init()
186 regmap_write(miig_rt, ICSSG_QUEUE_RESET_OFFSET, in icssg_miig_queues_init()
217 regmap_write(miig_rt, ICSSG_QUEUE_OFFSET + 4 * queue, in icssg_miig_queues_init()
464 regmap_update_bits(prueth->miig_rt, FDB_GEN_CFG1, SMEM_VLAN_OFFSET_MASK, in icssg_init_emac_mode()
475 icssg_class_set_host_mac_addr(prueth->miig_rt, mac); in icssg_init_emac_mode()
488 regmap_write(prueth->miig_rt, FDB_GEN_CFG2, FDB_EN_ALL); in icssg_init_fw_offload_mode()
517 regmap_update_bits(prueth->miig_rt, ICSSG_CFG_OFFSET, in icssg_config()
519 icssg_miig_set_interface_mode(prueth->miig_rt, slice, emac->phy_if); in icssg_config()
[all …]
A Dicssg_prueth_sr1.c159 val = icssg_rgmii_get_speed(prueth->miig_rt, slice); in icssg_config_set_speed_sr1()
164 val = icssg_rgmii_get_fullduplex(prueth->miig_rt, slice); in icssg_config_set_speed_sr1()
214 icssg_update_rgmii_cfg(prueth->miig_rt, emac); in emac_adjust_link_sr1()
499 icssg_class_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); in emac_ndo_open()
501 icssg_class_default(prueth->miig_rt, slice, 0, true); in emac_ndo_open()
665 icssg_class_disable(prueth->miig_rt, prueth_emac_slice(emac)); in emac_ndo_stop()
726 icssg_class_promiscuous_sr1(prueth->miig_rt, slice); in emac_ndo_set_rx_mode_sr1()
731 icssg_class_default(prueth->miig_rt, slice, 1, true); in emac_ndo_set_rx_mode_sr1()
735 icssg_class_default(prueth->miig_rt, slice, 0, true); in emac_ndo_set_rx_mode_sr1()
738 icssg_class_add_mcast_sr1(prueth->miig_rt, slice, ndev); in emac_ndo_set_rx_mode_sr1()
[all …]
A Dicssg_stats.c39 regmap_read(prueth->miig_rt, in emac_update_hardware_stats()
42 regmap_write(prueth->miig_rt, in emac_update_hardware_stats()
A Dicssg_prueth.c219 icssg_class_default(prueth->miig_rt, ICSS_SLICE0, 0, false); in prueth_emac_common_start()
220 icssg_class_default(prueth->miig_rt, ICSS_SLICE1, 0, false); in prueth_emac_common_start()
259 icssg_class_disable(prueth->miig_rt, ICSS_SLICE0); in prueth_emac_common_start()
260 icssg_class_disable(prueth->miig_rt, ICSS_SLICE1); in prueth_emac_common_start()
272 icssg_class_disable(prueth->miig_rt, ICSS_SLICE0); in prueth_emac_common_stop()
273 icssg_class_disable(prueth->miig_rt, ICSS_SLICE1); in prueth_emac_common_stop()
328 icssg_update_rgmii_cfg(prueth->miig_rt, emac); in emac_adjust_link()
714 icssg_class_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); in emac_ndo_open()
715 icssg_ft1_set_mac_addr(prueth->miig_rt, slice, emac->mac_addr); in emac_ndo_open()
1558 icssg_class_set_host_mac_addr(prueth->miig_rt, in prueth_netdevice_event()
[all …]

Completed in 18 milliseconds