Searched refs:min_clocks (Results 1 – 12 of 12) sorted by relevance
| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_dpmm/ |
| A D | dml2_dpmm_dcn4.c | 355 display_cfg->min_clocks.dcn4x.svp_prefetch.dcfclk_khz = 0; in map_soc_min_clocks_to_dpm_coarse_grained()
356 display_cfg->min_clocks.dcn4x.svp_prefetch.fclk_khz = 0; in map_soc_min_clocks_to_dpm_coarse_grained()
357 display_cfg->min_clocks.dcn4x.svp_prefetch.uclk_khz = 0; in map_soc_min_clocks_to_dpm_coarse_grained()
602 …if (in_out->programming->min_clocks.dcn4x.svp_prefetch.uclk_khz > in_out->programming->min_clocks.… in map_mode_to_soc_dpm()
603 …in_out->programming->min_clocks.dcn4x.active.uclk_khz = in_out->programming->min_clocks.dcn4x.svp_… in map_mode_to_soc_dpm()
605 …if (in_out->programming->min_clocks.dcn4x.svp_prefetch.fclk_khz > in_out->programming->min_clocks.… in map_mode_to_soc_dpm()
606 …in_out->programming->min_clocks.dcn4x.active.fclk_khz = in_out->programming->min_clocks.dcn4x.svp_… in map_mode_to_soc_dpm()
608 …if (in_out->programming->min_clocks.dcn4x.svp_prefetch.dcfclk_khz > in_out->programming->min_clock… in map_mode_to_soc_dpm()
609 …in_out->programming->min_clocks.dcn4x.active.dcfclk_khz = in_out->programming->min_clocks.dcn4x.sv… in map_mode_to_soc_dpm()
634 …out->programming->min_clocks.dcn4x.dispclk_khz, &in_out->programming->min_clocks.dcn4x.dpprefclk_k… in map_mode_to_soc_dpm()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| A D | dml21_translation_helper.c | 1154 …context->bw_ctx.bw.dcn.clk.dispclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
1155 …context->bw_ctx.bw.dcn.clk.dcfclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x… in dml21_copy_clocks_to_dc_state()
1156 …context->bw_ctx.bw.dcn.clk.dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4… in dml21_copy_clocks_to_dc_state()
1157 …context->bw_ctx.bw.dcn.clk.fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.a… in dml21_copy_clocks_to_dc_state()
1158 …context->bw_ctx.bw.dcn.clk.idle_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks… in dml21_copy_clocks_to_dc_state()
1159 …context->bw_ctx.bw.dcn.clk.idle_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dc… in dml21_copy_clocks_to_dc_state()
1160 ….clk.dcfclk_deep_sleep_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.deepsleep_… in dml21_copy_clocks_to_dc_state()
1163 …context->bw_ctx.bw.dcn.clk.dtbclk_en = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.… in dml21_copy_clocks_to_dc_state()
1164 …context->bw_ctx.bw.dcn.clk.ref_dtbclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.d… in dml21_copy_clocks_to_dc_state()
1165 …context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x… in dml21_copy_clocks_to_dc_state()
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| A D | dml21_utils.c | 230 pipe_ctx->plane_res.bw.dppclk_khz = pln_prog->min_clocks.dcn4x.dppclk_khz; in dml21_program_dc_pipe()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/inc/ |
| A D | dml_top_types.h | 222 } min_clocks; member
269 } min_clocks; member
409 } min_clocks; member
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| /drivers/gpu/drm/amd/pm/swsmu/smu11/ |
| A D | sienna_cichlid_ppt.c | 1833 struct smu_clocks min_clocks = {0}; in sienna_cichlid_notify_smc_display_config() local
1837 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in sienna_cichlid_notify_smc_display_config()
1838 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in sienna_cichlid_notify_smc_display_config()
1839 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in sienna_cichlid_notify_smc_display_config()
1843 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in sienna_cichlid_notify_smc_display_config()
1850 min_clocks.dcef_clock_in_sr/100, in sienna_cichlid_notify_smc_display_config()
1863 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in sienna_cichlid_notify_smc_display_config()
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| A D | navi10_ppt.c | 2131 struct smu_clocks min_clocks = {0}; in navi10_notify_smc_display_config() local
2135 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk; in navi10_notify_smc_display_config()
2136 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk; in navi10_notify_smc_display_config()
2137 min_clocks.memory_clock = smu->display_config->min_mem_set_clock; in navi10_notify_smc_display_config()
2141 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10; in navi10_notify_smc_display_config()
2148 min_clocks.dcef_clock_in_sr/100, in navi10_notify_smc_display_config()
2161 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0); in navi10_notify_smc_display_config()
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| /drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| A D | vega12_hwmgr.c | 1620 struct PP_Clocks min_clocks = {0}; in vega12_notify_smc_display_config_after_ps_adjustment() local
1630 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1631 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega12_notify_smc_display_config_after_ps_adjustment()
1632 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega12_notify_smc_display_config_after_ps_adjustment()
1636 clock_req.clock_freq_in_khz = min_clocks.dcefClock / 10; in vega12_notify_smc_display_config_after_ps_adjustment()
1642 min_clocks.dcefClockInSR / 100, in vega12_notify_smc_display_config_after_ps_adjustment()
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| A D | vega20_hwmgr.c | 2354 struct PP_Clocks min_clocks = {0}; in vega20_notify_smc_display_config_after_ps_adjustment() local
2358 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2359 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega20_notify_smc_display_config_after_ps_adjustment()
2360 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega20_notify_smc_display_config_after_ps_adjustment()
2364 clock_req.clock_freq_in_khz = min_clocks.dcefClock * 10; in vega20_notify_smc_display_config_after_ps_adjustment()
2369 min_clocks.dcefClockInSR / 100, in vega20_notify_smc_display_config_after_ps_adjustment()
2379 dpm_table->dpm_state.hard_min_level = min_clocks.memoryClock / 100; in vega20_notify_smc_display_config_after_ps_adjustment()
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| A D | vega10_hwmgr.c | 4106 struct PP_Clocks min_clocks = {0}; in vega10_notify_smc_display_config_after_ps_adjustment() local
4117 min_clocks.dcefClock = hwmgr->display_config->min_dcef_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()
4118 min_clocks.dcefClockInSR = hwmgr->display_config->min_dcef_deep_sleep_set_clk; in vega10_notify_smc_display_config_after_ps_adjustment()
4119 min_clocks.memoryClock = hwmgr->display_config->min_mem_set_clock; in vega10_notify_smc_display_config_after_ps_adjustment()
4122 if (dpm_table->dpm_levels[i].value == min_clocks.dcefClock) in vega10_notify_smc_display_config_after_ps_adjustment()
4132 min_clocks.dcefClockInSR / 100, in vega10_notify_smc_display_config_after_ps_adjustment()
4141 if (min_clocks.memoryClock != 0) { in vega10_notify_smc_display_config_after_ps_adjustment()
4142 idx = vega10_get_uclk_index(hwmgr, mclk_table, min_clocks.memoryClock); in vega10_notify_smc_display_config_after_ps_adjustment()
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| A D | smu7_hwmgr.c | 4096 struct PP_Clocks min_clocks = {0}; in smu7_find_dpm_states_clocks_in_dpm_table() local
4113 if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && in smu7_find_dpm_states_clocks_in_dpm_table()
4114 (min_clocks.engineClockInSR >= SMU7_MINIMUM_ENGINE_CLOCK || in smu7_find_dpm_states_clocks_in_dpm_table()
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| /drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| A D | dml2_core_dcn4.c | 561 …ams.min_clk_index = lookup_uclk_dpm_index_by_freq(in_out->programming->min_clocks.dcn4x.active.ucl… in core_dcn4_mode_programming()
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| A D | dml2_core_dcn4_calcs.c | 10374 mode_lib->mp.Dcfclk = programming->min_clocks.dcn4x.active.dcfclk_khz / 1000.0; in dml_core_mode_programming()
10375 mode_lib->mp.FabricClock = programming->min_clocks.dcn4x.active.fclk_khz / 1000.0; in dml_core_mode_programming()
10376 …mode_lib->mp.dram_bw_mbps = uclk_khz_to_dram_bw_mbps(programming->min_clocks.dcn4x.active.uclk_khz… in dml_core_mode_programming()
10377 mode_lib->mp.uclk_freq_mhz = programming->min_clocks.dcn4x.active.uclk_khz / 1000.0; in dml_core_mode_programming()
10378 mode_lib->mp.GlobalDPPCLK = programming->min_clocks.dcn4x.dpprefclk_khz / 1000.0; in dml_core_mode_programming()
10379 s->SOCCLK = (double)programming->min_clocks.dcn4x.socclk_khz / 1000; in dml_core_mode_programming()
10416 mode_lib->mp.Dppclk[k] = programming->plane_programming[k].min_clocks.dcn4x.dppclk_khz / 1000.0; in dml_core_mode_programming()
10422 …mode_lib->mp.DSCCLK[k] = programming->stream_programming[stream_index].min_clocks.dcn4x.dscclk_khz… in dml_core_mode_programming()
10426 mode_lib->mp.Dispclk = programming->min_clocks.dcn4x.dispclk_khz / 1000.0; in dml_core_mode_programming()
10427 mode_lib->mp.DCFCLKDeepSleep = programming->min_clocks.dcn4x.deepsleep_dcfclk_khz / 1000.0; in dml_core_mode_programming()
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